带LDN的的同步的预置数端子，并且带CLR的异步清零端

VHDL描述的时钟分频电路，用途广-VHDL description of the clock divider circuit, uses widely ...

利用matlab设计了一个切比雪夫滤波器，并且对滤波器性能进行了仿真分析。(Using the matlab design a chebyshev filter, and has carried on the simulation analysis on filter performance. )

说明：  5604FPGA驱动，能显示数字（5604里面为4个595）(5604 FPGA driver, able to display digital (5604 contains 4 595))

说明：  该程序使用Verilog语言产生LFM信号(The program uses Verilog language to generate LFM signals.)

用FPGA实现CRC算法，只用一个脉冲就能实现，比传统的移位算法大大节约时间-Using FPGA to achieve CRC algorithm, only one pulse will be able to realize, than the traditional algorithm greatly saving time shift

采用FPGA 来实现一个基于OFDM 技术 的通信系统中的基带数据处理部分，即调制解调器。其中发射部分的调制 器包括：信道编码（Reed-Solomon 编码），交织，星座映射，FFT 和插 入循环前缀等模块。(FPGA to implement a baseband data based on OFDM technology in the communication system processing section, namely modem. Transmitter modulator includes: channel coding (Reed-Solomon coding), interleaving, constellation mapping, FFT and insert the cyclic prefix modules.)

交通灯的ＶＥＲＩＬＯＧ实现，含详细中文注释．-Verilog realize traffic lights, with detailed notes in Chinese.

说明：  基于FPGA的游戏实例，开发板为Xilinx的basys3，VGA显示(Basys3, VGA Display of Xilinx Development Board Based on Game Example of FPGA)

eDP接口TFT-LCD显示驱动原码（verilog+c）(eDP Interface TFT-LCD display driver source code (verilog+c))

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