Xilinx的FPGA开发DEMO例程，功能相对来说比较全面，适合新手参考。...

四位拨妞开关作为输入，当输入值变化时将其转化成两位输出(The four DIP Niu switch as an input, when the input value changes, be converted into two output)

AD7606采集代码，用于verilog 驱动 AD7606 adc SPI 串口方式(AD7606 acquisition code, used for Verilog drive AD7606 ADC SPI serial mode)

这是个关于verilog入门的文档，有同志对verilog感兴趣，可以下载此文档，以供参考。(This is a verilog entry on the document, there are comrades of the verilog interested, you can download this document for reference.)

flii adder wave form 3

运用matlab实现fft变换，用于地震资料频谱分析！(FFT transform)

verilog测试，fpga测试片外sramis61lv25616，256个k个字，16位，比较难调(it is fpga is 61lv25616 simple verilog program,complete sram read and write.it can read and write .)

在quartus平台下，并使用verillog hdl编写的时钟分频仿真(In quartus platform and use verillog hdl write clock divider simulation)

基于VHDL的RS232通讯程序,包含完整的源代码,锁脚文件以及下载文件,可直接下载使用-VHDL based on the RS232 communication procedures, including complete source code, locking pin, as well as download files documents can be directly downloaded using

8位加法器源代码，vivado实现编写。(8 adder Source, vivado achieve write.)

SAA7113 ＦＰＧＡ开发实例，非常经典(The SAA7113 FPGA development examples, very classic)