USB IPcoreIP核 包含文档(带说明)

蛋蛋助手,可以动态配置生成代码格式,方便ORM或或程序员的生成工作 ，经测试 (Egg assistant, can be dynamically configured to generate code format, convenient ORM, or programmer generation work, tested)

说明：  使用DDR3IP核进行仿真，写入读取数据(Using DDR3IP core to simulate, write and read data)

用verilog语言编写的4位算术逻辑单元ALU,功能参考74181，包含.v文件以及测试用.vwf文件(Verilog languages with four arithmetic logic unit ALU, functional reference to 74,181, including. V documents and testing. Vwf document)

4位全加法器的modelsim工程带testbench(Four full-adder modelsim project with testbench)

VHDL CODE FOR SQUARE WAVE GENERATOR

频率计，ＶＥＲＩＬＯＧ代码，含详细　中文注释．-Cymometer, VERILOG code, containing a detailed Chinese Notes.

基于fpga的多功能数字时钟的实现，已经编译过了，绝对可行-fpga-baseed clock

自己做的数码管显示的时钟 一个非常简单的FPGA时钟 用累加做的(To do their own digital display clock of the FPGA clock is a very simple to do with the cumulative)

刚写的一个44键盘程序，调了好多天才调出来，给大家提供参考。-Just write a 44 keyboard program, tune out of tune a lot of talent to give you a reference.

verilog的入门级别的例子（转载）-Verilog entry-level examples (reproduced)