eab_vhdl

this project is based on 2*1 and 4*1 multiplexer and 1*2 and 1*4 demultiplexer using vhdl.this is the 100 correct code,reference is taken from book digital electrionics written by anand kumar.please use quatrus to access this code.this code can be used for the final year project for engineering. Here dataflow techniques and behavioural -this project is based on 2*1 and 4*1 multiplexer and 1*2 and 1*4 demultiplexer using vhdl.this is the 100 correct code,reference is taken from book digital electrionics written by anand kumar.please use quatrus to access this code.this code can be used for the final year project for engineering. Here dataflow techniques and behavioural

实现有限域中乘法，输入二个普通二级制数，输出在本原多项式的乘法结果(Achieve limited multiplication field, enter the number of two-tier system of two ordinary output in primitive polynomial multiplication results)

七人抢答器 可做课程设计 能仿真 一人抢完其他人锁定-qiren qiangdaqi ke fangzhen

基于FPGA的自适应滤波器的实现。采用Verilog编程，2阶滤波器。(FPGA-based realization of the adaptive filter. Using Verilog programming, 2-order filter.)

应用背景为了实现良好的压缩性能，相关性颜色分量RGB颜色空间转换到去相关的色彩空间首先减少。在基线JPEG，一个RGB图像转化成亮度chrominancc如YCbCr颜色空间。将图像的亮度色度空间的优势的亮度和色度分量非常不相关彼此之间。此外，色度通道包含大量冗余信息可以很容易地被采样不牺牲任何视觉质量对于重建图像。从RGB到YCbCr的转换，是基于以下的数学表达：关键技术应用DCT变换，将图像划分成8´8像素块。如果原始图像的宽度或高度是不能被8整除，编码器必须整除。8´8块进行处理，从左到右，从上到下。和公司；及；及；及；及；及；及；及；及；DCT变换的像素值的空间频率。这些空间频率是非常相关的细节目前在一个图像的水平。高空间频率对应于高层次的细节，而较低频率对应于较低的细节层次。数学定义DCT是：

这是执行高速的代码通用异步收发器代码是用VHDL写的语言.UART是一种在传输端进行并行输入和串行输出，在接收端进行串行输入和并行输出的算法。

morris mano basic vhdl code in ise

熟悉IIC协议总线协议，采用IIC总线对图像采集传感器寄存器进行配置，并转换为RGB565格式。 利用异步FIFO完成从摄像头输出端到SDRAM 和SDRAM 到VGA 接口各跨时钟域信号的传输和处理。 利用 SDRAM 接口模块的设计，实现了刷新、读写等操作；为提高SDRAM 的读写带宽，均采用突发连续读写数据方式；并采用乒乓操作实现 CMOS 摄像头与VGA的帧率匹配。 利用双线性插值方法实现对图像640×480到1024×768的放大操作。 完成VGA显示接口设计。(Familiar with IIC protocol bus protocol, IIC bus is used to configure the register of image acquisition sensor and convert it into RGB565 format. Asynchronous FIFO is used to transmit and process signals across clock domain from camera output to SDRAM and SDRAM to VGA interface. With the design of SDRAM interface module, refresh, read and write operations are realized. In order to improve the read and write bandwidth of SDRAM, burst continuous read and write data mode is adopted, and table tennis operation is used to achieve frame rate matching between CMOS camera and VGA. The bilinear interpolation method is used to enlarge the image from 640*480 to 1024*768. Complete the VGA display interface design.)

VHDL由简单存储器，计数器等搭建最终实现8位的cpu设计(VHDL realization 8 of cpu design)

产生svpwm波形，可以参考下载,以便学习交流(gennerate SVPWM wave)