eab_vhdl

FIR滤波器的VHDL语言实现-The implement of FIR Filter based on VHDL

由忆阻器机制设计蕴含逻辑，内含testbench仿真文件(Design implied logic by memristor mechanism, including testbench simulation file)

XCZ7035的硬件平台使用说明 包括USB接口(XCZ7035 hardware platform instructions Including USB interface)

ASIC设计中常用的运算模块，如加减，常系数乘法，截断，饱和等。(some modules used in ASIC design.)

收集了目前关于FPGA设计的论坛，大家如果有什么疑问，可以到这些论坛上求助。-The collection of the current design of the forum on the FPGA, there is little doubt if the U.S. can go to for help on these forums.

用Verilog实现的 哈佛结构的简单指令集CPU程序，由ALU、地址译码器、指令译码器等部分组成(Part of a simple instruction Verilog realize the Harvard architecture CPU program set by the ALU, address decoder, an instruction decoder, etc.)

控制三相步进电机及光电编码器的采集,当电机停止时,保证三相里面只有一相相通,防止停止时电流过大.(Control three-phase stepper motor and optical encoder collection, when the motor stops to ensure that only one phase of three-phase inside the heart, and to prevent too much current is stopped.)

A latch3 written in VHDL.

设计一个具有同步置1，异步清零的D触发器。 设计一个类似74LS160的计数器(Design an D trigger with synchronous reset 1 and asynchronous reset. Design a counter like 74LS160.)