用于FPGA的变长编码算法的HDL编码，包括VHDL及Verilog代码。可用于JPEG及MPEG压缩算法。...

一款在Verilog实现的吃豆人游戏，采用VGA接口，在Nexys3开发板上运行无误。(A pac-man game implemented via Verilog, using VGA interface, perfectly run on Nexys 3)

基于cordic算法的DDS的Verilog代码。经过仿真验证，绝对可靠。(Based on cordic algorithm DDS Verilog code. Through the simulation, is absolutely reliable.)

基于VHDL语言的设计8位CISC微处理器实例-VHDL design language based on 8-bit CISC microprocessor examples

AHB master monitor for verification

此文档包含 VHDL 的Vedic 乘数的详细内容。 它内容Vedic 乘数过程的详细的解释。

SDRAM控制器源码，内含完整的控制器verilog源代码和测试代码，超值哈。(This readme file for the SDR SDRAM Controller includes information that was not incorporated into the SDR SDRAM Controller White Paper v1.1.)

实现I2C协议下EEPROM存储的数据读写控制(Under I2C protocol to achieve read and write data stored in EEPROM control)

verilog code for bus controller

低密度校验码 ，很好用的代码，功能已经实现编码和译码(fpga ldpc)

基于FPGA的希尔伯特变化的verilog代码(Hilbert change verilog code)