FPGA数字钟

d5m的DE2驱动Verilog HDL (d5m driven on DE2 by Verilog HDL )

Synthetic Aperture Radar (SAR) imaging simulation target, Using wavelet denoising thought, LCMV optimization design array signal processing.

DDS VHDL include everything of dds AD9914

说明：  用uvm验证方法学验证异步fifo，文件包括异步FIFOrtl代码和uvm组件(Verification of asynchronous FIFO with UVM)

基于fpga的uart串口通信协议，64位数据(Uart communication protocol based on fpga, 64-bit data)

usb读取，仅供参考，在实际应用中要更改以下数据。(Read usb data)

QUARTUSII 9.0 下的三级流水线中值滤波工程，vhdl源程序等。可用于fpga做图像预处理。(the three stage pipeline median filter project under QUARTUSII 9 , VHDL source program. which can be used by FPGA to do image preprocessing. )

fpga高手设计实战真经100则,最新的FPGA英文书籍，值得参考学习(100 Power Tips for FPGA Designers，The new FPGA English books, worth learning)

说明：  I2C MASTER DESIGNED by Verilog

实现psk调制解调，vhdl代码，仿真文件也有(psk shixian tiaozhiyujietiao)