录像带上 ALtera DE2 教育委员会，旋风 2

利用DE2115开发板进行串口通信，完成串口的发送，将板子上的滑动按键的状态通过串口传至上位机，并且在LED上显示。

GMSK vhdl generated from simulink

说明：  ZYNQ FPGA XC7Z035纯verilog配置AD9361 基于VIVADO2016.4工程(ZYNQ FPGA XC7Z035 Pure Verilog Configuration AD9361 Based on VIVADO 2016.4 Project)

说明：  uvm lab代码以及uvm1.2源码，带有使用说明文档，可以照着文档一步一步深入了解uvm代码。(The code of UVM lab and the source code of uvm1.2 are provided with instruction documents. You can follow the documents step by step to understand the UVM code.)

说明：  用VHDL语言实现电子钟(Using VHDL language electronic bell)

FIR滤波器的VHDL源代码及测试文件，已通过编译仿真，绝对正确。(FIR filter VHDL source code and test files, has passed the compiled simulation, absolutely correct.)

假设每个从设备中有可访问APB寄存器16个，位宽均为32比特，16个寄存器的访问地址计算方式为 基址 +　寄存器编号左移２位（byte 偏移）(Assuming that there are 16 accessible APB registers in each slave device, the bit width is 32 bits, and the access address of 16 registers is calculated by base address + register number left shift 2 bits (byte offset).)

Task4 for learning verilog

altear max10 adc demo，实验使用了2个adc，最大支持18路adc(altear max 10 demo with 2 adc， max support 18 channel adc)

用fpga实现的连连看游戏，功能还不完善，不过可以借鉴。(Realize with FPGA Lianliankan game, function is not perfect, but can be used for reference.)