本文提供了一个CMOS控制器，使Nios II可以利用C.

VHDL_count 从 0 到 9 4 7 段 LED 显示器 (đếm 0 đến 9 hiển 施耐 4 带领 7 đoạn)

PIC单片机学习软件及其资料，入门到精通(PIC MCU learning software and its information, entry to proficiency)

计数器的程序，eda编程用的，vhdl语言编程，大家下载看看吧(Program counter, eda programming used, vhdl programming )

控制ADV212 压缩的源代码 使用xilinx edk开发环境(adv 212 controller, using xilinx edk)

HDLC的一些相关文档，可能对HDLC设计有很大的帮助！-HDLC some relevant documents, HDLC design may be very helpful!

W elcome to X CELL, the new Xilinx customer newsletter. By sending us your development system registration card you automatically became n charter subscriber to this quarterly publication. It is our intent to make this an informative, easy to read, responsive and-hopefully- interactive newsletter. We want to supply you with early and correct information, tell you about the status of our products and about our plans, about bugs and their workarounds, give you applications ideas and convey to you some of the en thusiasm that we feel for our Programmable Gate Arrays. If you have questions or suggestions, please send them to me. II Letters to the Editor make a newsletter more lively. Peter Alfke, Editor

说明：  this describes building spi block on verilog hdl and programming them on an fpga device

这时一个数字钟的VHDL程序，有计时、校时、整点报时功能，很适合做EDA设计之用-When a digital clock in VHDL procedures, time, school hours, the whole point timekeeping function, it is suitable for use in EDA Design

一个简单的千兆以太网UDP协议的实现,可以实现数据的收发和ARP，实现PC端与FPGA的以太网通信(A simple implementation of Gigabit Ethernet UDP protocol can realize data sending and receiving and ARP, and realize Ethernet communication between PC and FPGA.)

RS码的FPGA实现，verilog语言形式，好参考资料(FPGA realization of RS code, verilog language form, a good reference)