本文提供了一个CMOS控制器，使Nios II可以利用C.

mimo—ofdm线性卷积，实现输入的800位宽的数据同两个序列的卷积(Mimo- ofdm linear convolution 800 bits wide input data with the convolution of two sequences )

3X3矩阵乘法的VHDL程序实现！对初学者有很大的帮助！-3X3 matrix multiplication VHDL program! For beginners is a great help!

采用VHDL语言实现基于ＢＭ算法的ＲＳ译码器，附件为整个工程文件，内附波形仿真图。程序在QUARTUS II 9.0下仿真通过

同步串行数据发送电路SSDT的基本功能是将并行数据转换成串行数据并进行同步发送。系统写入和读出时序完全兼容Intel8086时序。 系统以同步信号开始连续发送四个字节，在发送中出现5个1时插入一个0，在四个数据发送结束而下一次同步没有开始之前，发送7FH，这时中间不需要插入零 -synchronous serial data transmission circuit SSDT the basic function is to convert parallel data into serial and the same this step. System write and read sequential fully compatible Intel8086 timing. Synchronized signal system to start sending four consecutive bytes, in this emerging 5 1:00 insert a 0, at the end of four data sent and the next synchronization not started before, sending seven FH, then the middle is not inserted

利用LPM_MUIT宏模块设计一个四位数据乘法器(Use LPM_MUIT macro module design a four data Multiplier)

quartusII的环境下的基于Ep3C10144的KeyBoard程序-quartesII of the environment based on the KeyBoard program Ep3C10144

用于FPGA的量化算法的HDL编码，包括VHDL及Verilog代码。可用于JPEG及MPEG压缩算法。-Quantitative algorithm for FPGA HDL coding, including VHDL and Verilog code. Can be used in JPEG and MPEG compression algorithms.

SMBus控制器的VHDL源码程序，适用于Quartus2，ISE等开发环境。(The SMBus controller VHDL source code procedures applicable to Quartus2 ISE development environment.)

ddr3使用教学(DDR3 using teaching)

使用Altera公司的FPGA进行VHDL开发。使用quartus2 9.0软件在EP1C3T144C8开发板上用硬件描述语言实现一个ROM存储器。-The use of Altera" s FPGA-VHDL development. Use quartus2 9.0 software EP1C3T144C8 development board with hardware description language to achieve a ROM memory.