Verilog HDL系列和转换的准备。我用电流输出类型。股份有限公司...

说明：  用于实现上位机与下位机之间通过RS232协议来进行通讯。(It is used to realize communication between upper computer and lower computer through RS232 protocol.)

CSS配合jquery制作完美漂亮的时钟，貌似在IE8下时钟不能获取时间啊！支持ie9、chrome、safari、firefox、opera （Chrome显示效果最佳，IE9下时钟无法工作）日历和骰子是原创，CSS3时钟并非原创但经过改良支持opera。数字日历的兼容性不错，圆形时钟就差点了，也希望一起交流，共同改进。(CSS with the jquery make perfect beautiful clock, seemingly in IE8 under the clock can not get the time ah! Support ie9, chrome, safari, firefox, opera (Chrome show the best results, the clock does not work under IE9) calendar and dice is original, CSS3 clock is not original but after improved support opera. Digital calendar compatibility is good, almost round the clock on, and also hope together, and work together to improve.)

VIP FPGA板的配套例子，这个是VGA格式lcd液晶屏幕显示用。(VIP board supporting example of this is the VGA format PREVIEW.)

LDPC码的FPGA实现，大家相互学习下。。(the code of LDPC implementation by FPGA)

Eliminate the program of key bounce

本代码主要功能是PPM解码，采用Verilog语言，通过移位寄存器和组合电路实现解码。(The main function of this code is PPM decoding.)

该部分的主要功能是完成基于FPGA的polar码SC译码。(The main function of this part is to complete the FPGA-based polar code SC decoding.)

用verilog语言编写的步进电机加减速控制算法，可选择梯形曲线或S型曲线算法(Verilog language stepper motor acceleration and deceleration control algorithm, you can choose the trapezoidal curve or S-curve algorithm)

- RS码是Reed-Solomon 码（理德－所罗门码）的简称，它是一类非二进制BCH码，在RS码中，输入信号分成k·m比特一组，每组包括k个符号，每个符号由m个比特组成。(- RS code is a Reed-Solomon code (Reed- Solomon codes) for short, is a non-binary BCH code, the RS code, the input signal is divided into a set of k · m bits, each including k symbols, each symbol consists of m bits.)

This is code of UVM CALLBACK function.