verilog 设计流水灯

多功能数字钟，在quartusII软件平台上实现的verilog源代码。大家试试看。(Multifunctional digital clock in quartusII software platform to achieve the verilog source code. We try.)

Programmable IIR Filter written in Verilog and its respective modules.

这是一个基于车租车计费器的模拟计算系统，用VHDL语言实现(This is a car rental billing based on the simulation system, using VHDL language)

PD里面的4B5B编码，欢迎使用~~~~~~~~~~~~~~~~~(4B5B code in PD3.0 or USB3.0, welcome to use~~~~~~~~~~~~~~)

SPI读写AD9361，通过串口回读关键寄存器读写是否正确。(SPI reads and writes AD9361, reads and writes the key registers correctly through the serial port.)

8位并行输入的数转换成串行输出，是基于高级硬件编程语言VHDL编写的。(8-bit parallel input into serial output digital conversion is based on the high-level hardware programming language VHDL prepared.)

一个简单的后台模板，主要为贵金属直播室有喊单等功能类型的。 ps：由于涉及到iframe本地跨域问题，因此查看时请在服务器上进行审阅。(A simple background template, mainly for the precious metal living room, such as the type of function. PS: as a result of the local cross domain problem involved in the iframe, so check it out on the server.)

自己写的7人表决器的verilog程序，实现4人以上通过则通过的功能。(Seven people to write their own voting machine verilog program to achieve four or more people pass through function.)

说明：  用于FPGA的I2S接收模块，仅供学习和参考(audio-i2s receive.use fpga.)

FPGA设计中的时序分析及异步设计注意事项 (FPGA design timing analysis and design considerations for asynchronous)