串行至并行转换器 UVM 代码

上海交大关于基于FPGA的DSCDMA的实现的毕业设计(Shanghai Jiaotong University based the FPGA DSCDMA, achieve graduation design)

多相抽取滤波器。分四相，两倍抽取，采用16阶FIR滤波器实现(Polyphase decimation filters. Divided into four phases, extracted twice using 16-order FIR filter implementation)

VHDL Vendingmachine source

说明：  汉明码学习，以（7，4）为例，仿真正常。(Hamming code learning, taking (7, 4) as an example, the simulation is normal.)

说明：  运用VHDL描述函数发生器的各个波形，可有构成多功能函数发生器。(VHDL description of the use of various function generator waveforms, can constitute a multi-purpose function generator.)

Verilog UART is written in this file

Verilog使用$random()函數簡單範例(Verilog using the $ random () function of a simple example)

xilinx的zed板详细开发资料，对初学者和开发人员都有帮助(The Xilinx zed board detailed development information, helpful for beginners and developers)

turbo码的编码程序,verilog HDL,在ISE环境中(turbo code encoding process)

说明：  简易信号发生器，可以实现简单的信号实现，任意波编辑，通过FPGA的verilog语言实现功能，自测可以正常使用。(Simple signal generator, can realize simple signal realization, arbitrary wave editing, through FPGA Verilog language function, self-test can be used normally.)