flv的vhdl教学文件:在线调试 自己慢慢欣赏吧

说明：  使用vivado和Xilinx开发板实现抢答器，开发板为Xilinx Artix-7(Using vivado and Xilinx development board to achieve the responder, the development board is Xilinx artix-7)

verilog_ad0809 cpld control

四阶数字滤波器 用不同的算法设计数字滤波器，并且有详细的是用方法(Fourth-order digital filter design with a different digital filter algorithms and a detailed method is)

dct实现verilog hdl的数字图像处理，源代码(dct achieve verilog hdl digital image processing, source code)

ofdm的verilog程序 利用ＦＰＧＡ实现-OFDM FPGA using the Verilog procedures realize

时钟分频代码，PWM产生 RTL 源代码。(clock divider，PWM generator RTL Source Code)

generate sine wave. Inputs : Amplitude, phasein, frequency

FPGA设计频率计全套资料，我希望对大家啊好似有用的-FPGA design of a full set of frequency data, I hope all of you ah like useful

基于NIOS的CF卡应用(包括了软件和硬件),ALTERA的IP库中只提供了底层的硬件寄存器描述头文件.这是个基于IP核HAL的软件,以及相应的硬件设计示例.-NIOS based on the CF card applications (including the software and hardware), ALTERA the IP library provides only the bottom of the first document describes the hardware registers. This is a HAL-based IP core of the software, hardware design and the corresponding sample.

本实验实现PS/2接口与RS-232接口的数据传输， PS/2键盘上按下按键，可以通过RS-232自动传送到主机的串口调试终端上（sscom32.exe）； 并在数据接收区显示接收到的字符。 串口调试终端的设置：波特率115200，一个停止位，无校验位。-Realize this experiment, PS/2 interface with RS-232 data interface, PS/2 keyboard to press the button, through RS-232 automatic transmission to the host serial debug terminal (sscom32.exe) and data receiving display received characters. Serial debug terminal settings: 115200 baud rate, one stop bit, no parity bit.