CH4CH2CH1VHDL 数字电路参考书所有程序5

基于FPGA的快速傅里叶变换。使用ISE软件以及MATLAB验证。(FFT based on FPGA)

说明：  常系数有限域乘法器，verilog DHL源码(Constant coefficient finite field multiplier, verilog DHL source)

Run-Length Encoder Example: Input Sequence (hexadecimal format): 0A, 14, 14, 14, 14, 14, 14, 14, 56, 56, 56, 56, 56, 32, 32, 07 Output Sequence (hexadecimal format): 0A, 14, 87, 56, 85, 32, 32, 07

说明：  采用vhdl语言编写的卷积编码（2.1.7），通过调试可直接下载使用(Convolution using vhdl language code (2.1.7) can be directly downloaded through the use of debugging)

该例子是基于sopc的IIC总线设计完整设计，分为硬件和软件部分，软件部分是用c语言编写的。该项目是个以完成的项目，据有较高的参考和经济价值。该例子是原来做过的项目。 整个项目是在Quartus II 7.0和nios IDE环境下开发。 (This example is based on the IIC bus design sopc complete design, divided into hardware and software, the software part is written in c language. The project is to complete the project, according to the reference and a higher economic value. The example is a project originally done. The whole project is in the Quartus II 7.0 and the nios IDE development environment.)

关于一个串行数据输入 根据时序将数据分两路输出的程序 -on a serial data input timing will be based on output data using two procedures

在Xilinx开发环境ISE13.2上用MIG产生的DDR3 SDRAM控制器，里面生成了Core，可用于DDR3读写控制(On the Xilinx development environment ISE13.2 generated with MIG DDR3 SDRAM controller, which generates the Core, DDR3 can be used to read and write control)

关于一款线阵CCD TCD1206UD 的驱动设计，波形符合工作要求(On how the system in SOPC using HDL language development from a custom IP core)

ldpc编码器ru算法的verilog语言的完整实现，希望对您有用(ldpc encoder, RU, VERILOG，altera)

数字密码锁的vhdl实现，包括设置密码，修改密码，报警。