CH4CH2CH1VHDL 数字电路参考书所有程序5

基于fpga的多功能数字时钟的实现，已经编译过了，绝对可行-fpga-baseed clock

Hynix公司8M Byte SDR SDRAM的Verilog语言仿真实现-Hynix" s 8M Byte SDR SDRAM Simulation of the Verilog language

使用 c languageit 的 16 点基 2 fft 代码将 16 点时间域序列转换为频率域

at070tn83 800x480 tft lcd verilog 測試 quartus 文件 (800x480 tft lcd at070tn83 testing project file)

build synthesizer on a de2 dev fpga board

交通灯控制器的VHDL设计,能控制十字路口的红绿灯转换,通过目标芯片EPF10KLC84-4验证-Traffic lights controller VHDL design, can be controlled by traffic lights at the crossroads of the conversion, through the target chips EPF10KLC84-4 verification

说明：  libero soc工程，实现通过串口接收到单字节数据后并返回发送给上位机(Libero SOC project, which realizes receiving single byte data through serial port and sending it back to host computer)

altera 的reed solomn 设计(reed solomn design from altera)

-- M68008 Address Decoder -- Address decoder for the m68008 -- asbar must be 0 to enable any output -- csbar(0) : X"00000" to X"01FFF" -- csbar(1) : X"40000" to X"43FFF" -- csbar(2) : X"08000" to X"0AFFF" -- csbar(3) : X"E0000" to X"E01FF" -- download from www.pld.com.cn & www.fpga.com.cn --- M68008 Address Decoder-- Address decod er for the m68008-- 0 asbar must be to enable any o utput-- csbar (0) : X "00000" to X "01FFF"-- csbar (1) : X "40000" to X "43FFF"-- csbar (2) : X "08000" to X "0AFFF"-- csbar (3) : X "E0000" to X "E01FF"-- download from www.pld. com.cn

这是使用VHDL语言编写的密码锁程序,供大家参考-This is the use of the VHDL code lock preparation procedures for reference