a vhdl_program used for flat detect

说明：  Use of Kalman and EKF on two-phase permanent magnet synchronous motor of the state estimate CDCDCDCDCCC

任意基数分频VERILOG代码，经过了编译，可以修改数字改变分频。-Arbitrary base frequency Verilog code, after compilation, the figures can be amended to change the frequency.

vhdl编写的fifo程序-VHDL procedures prepared by the fifo

自动售卖机的设计，有源代码，希望对大家有用-Vending machine design, source code, in the hope that useful

usb3.0 物理层仿真，verilog编程(Start the physical simulation)

用DE0开发板实现电话计费器，基本功能：可设置通话模式，能初始化话费余额，拨动开关可进入通话模式，并根据通话时间和相应通话模式扣除相应的费用。通话过程中能够通过开关切换显示通话时间和话费余额，并可暂停通话。压缩包里有详细的WORD文档的说明，包括波形仿真和DE0的引脚功能介绍。(Implemented by DE0 board telephone billing, basic function: to set the call mode, you can initiate credit balance, toggle switch into the talk mode, and deduct the cost of a call based on call time and the corresponding mode. Call talk time and can be displayed by switching credit balance, and mute. Compression bag has a detailed description of WORD documents, including the waveform simulation and DE0 pin function description.)

说明：  高清电子书4本合集-Verilog HDL数字系统设计教程4本合集(Digital circuit design Verilog HDL digital system design)

fifo的代码,经过测试可以使用，很有用处，可以放心使用(a fifo module,the code has been tested and it is usefull)

说明：  there's a clock divider for DE2 altra board clock (50MHz)

CH4CH2CH1VHDL 数字电路参考书所有程序5-CH4CH2CH1VHDL digital circuit reference all proceedings 5