a vhdl_program used for flat detect

这是兼容的8051 VHDL CPU实现，应该不算侵权吧。 上帝保佑！-This is compatible CPU 8051 VHDL, it is not a tort. God bless!

xilinx公司的FPGA实现数字视频信号处理器。语言是VHDL。-Xilinx FPGA to achieve the company

整理的网上关于LCD12864(ST7920控制器）的串并口程序，已在stc89c52rd+11.0592MHz的情况下测试通过(Finishing line on LCD12864 (ST7920 controller) serial and parallel programs, in the case of stc89c52rd+11.0592 MHz test)

用于FPGA的学习，大家值得借鉴，可以好好学习一下(this is for fpga and you can use this.)

该代码实现了FPGA对USB芯片68013的读写，语言是VERLOD，试验通过。(The code to achieve the FPGA read and write 68013 on the USB chip, the language is VERLOD, through the test. )

用VHDL语言在CPLD上实现串行通信-using VHDL on the CPLD Serial Communication

用VHDL语言实现8-3线编码器，16-4线编码器-VHDL language used to achieve 8-3 line encoder ,16-4-wire encoder

五级流水线CPU实现（带Hazard），还没来得及实现Cache求高人指教(pipeline CPU with Hazard)

USB Blaster full production data

说明：  misp，五级流水源码，实现一个建议的cpu(Misp, five-stage flow source code, implementation of a recommended CPU)