Using VHDL programming asynchronous FIFO procedure can be run by the debugger

结合XILINXCPLD所做的模拟RS232通信verilog源程序-XILINXCPLD combine the simulation RS232 communication Verilog source

Some useful PicoBlaze sources.

数字电压表的实现，VHDL语言实现，AD采用TLC549，通过学习，了解AD采集过程(The realization of digital voltage meter, VHDL language, AD using TLC549, by learning to understand the acquisition process AD)

这是基数 4 修改 Booth 型乘法器为 8 位。它可以用于任何大小的操作数的乘法......

一路24位计数器,cpu可直接读写计数器的计数值.-All the way 24-bit counters, cpu can be directly read and write the total value counters.

浙江大学体系结构实验课代码 实现5级流水线带有停顿，旁路和控制竞争的处理。(Experimental Architecture, Zhejiang University course code with a pause 5-stage pipeline, bypassing the treatment and control of competition.)

讲述了全数字信号发生器部分频率值测算的表格(Full digital signal generator frequency value calculation form )

用VHDL语言设计篮球24秒可控计时器功能说明：1.具有24秒计时、显示功能；              2.设置外部按键，完成清零、暂停、恢复控制；              3.24秒倒计时，时间间隔为1s；               4.时间到后发出报警信号，并在3s后解除。

This tutorial introduce VHDL code for clock pulse and 4-bit counter. With four bits, the counter count from 0 to 15. The timing of the counter is controlled by a clock signal. There will be a clear signal which can reset the counter value.

无线通信中接收侧自动增益控制模块的vhdl代码实现(Receive side of the AGC module vhdl code for wireless communications)