Using VHDL programming asynchronous FIFO procedure can be run by the debugger

spartan-3e vhdl fpga 输入用滑动按钮代替 输出用led代替(spartan-3e VHDL fpga input with sliding button instead of the output with led instead)

用于实现上位机与下位机之间通过RS232协议来进行通讯。(It is used to realize communication between upper computer and lower computer through RS232 protocol.)

针对FPGA一个实现vga显示的很好的例程，vhdl语言编写。-FPGA realize for a good vga display routines, vhdl language.

由verilog编写的乘法器，通过两个文件的调用实现。由于子模块的调用使得程序简化了许多。(Prepared by the Verilog multiplier, through the realization of the two documents call. As the sub-modules to simplify the procedure call makes a lot.)

ICA (Principal Component Analysis) algorithm and procedures, GSM is GMSK modulation signal generation, On neural network control.

8级cordic 算法verilog (8 cordic algorithm verilog)

基于FPGA的温度控制系统 VHDL 数码管显示温度 ds1820 温度报警(The temperature control system based on FPGA VHDL digital display temperature ds1820 temperature alarm)

xilinx FPGA技术详解,从设计流程到设计注意点(xilinx FPGA technology Detailed Design points, from the design process to)

VHDL operators basics

利用LMP的20bit counter,比自带的cout进位要快的多。已经同错综合和时序仿真。-LMP