基于EPM1270

说明：  DDS的基本原理主要由五部分组成，分别是；相位累加器，正弦波形存储器，数模转换器，低通滤波器和时钟，将相位累加器输出的数据作为地址，用来查询表的数据，将取出的正弦数据通过数模转换器输出模拟信号，模拟信号再通过一个低通滤波器输出纯净的正弦波信号。(The basic principle of DDS is mainly composed of five parts: phase accumulator, sinusoidal waveform memory, digital to analog converter, low-pass filter and clock. The output data of phase accumulator is used as address to query the data of table. The extracted sinusoidal data is output analog signal through digital analog converter, and the analog signal is output pure sine through a low-pass filter Wave signal.)

说明：  串口！ 这是一个使用的通信程序 ， 非常好用。(serial port Serial port! This is a communication program used, very useful.)

基于stm32开发平台的，模拟ad采样程序设计，可直接下载使用(stm32 zhijiexiazaishiyong)

一位全加器的VHDL源码与TEST BENCH.XILINX下通过(A full adder and the VHDL source code through TEST BENCH.XILINX)

这个

FPGA的仿真实例，Verilog代码编写，过程详尽，代码易懂。第三个文档-FPGA simulation examples, Verilog coding, the process in detail, code easy to understand. The third document

verlog hdl无刷电机控制程序,已在modelsim仿真-verlog hdl brushless motor control procedures have been in ModelSim Simulation

我们的设计是用一个FSM控制器来控制发送什么命令，flash模块判断FSM发送过来的state信号来选择应该执行什么操作，当命令写入或者读出后，会发送一个flag_done命令，这个命令让我们判断上个指令是否完成，如果完成后FAM将发送下一个命令.(Our design uses a FSM controller to control what commands are sent. The flash module judges the state signal sent by the FSM to select what operation should be performed. When the command is written or read out, a flag_done command is sent. This command lets us judge whether the last word is finished or if the FAM will be sent after completion. The next command)

这是在 vhdl 的简单循环的拳头在后进先出队列。缓冲区的大小和数据大小可以通过 N 和 W 的参数配置。队列最前面的是可用输出数据。两个信号控制写入和读取数据。如果缓冲区是空的还是满的两个输出信号信息。

本源码为Nios II的开发示例,主要演示Nios II的定时中断器的应用。开发环境QuartusII。 本示例十分经典，对基于SOPC开发的FPGA初学者有很大帮助。-The source code for the Nios II development of an example, the main demonstration Nios II interrupt timing device applications. Development environment QuartusII. This example is very classic, FPGA-based SOPC development of great help for beginners.