串口FIFO接口设计

说明：  华为经典设计全套入门技巧，面试经验，设计技巧(Huawei Classic Design Complete Introduction Skills, Interview Experience, Design Skills)

qsys-niosii-triple-speed-ethernet-3c120-v10-1

说明：  实现24小时计时，因为位数不够，这里是12进位，可自行调整进位数(Realize 24-hour timing, because the number of digits is not enough, here is 12 carry, you can adjust the carry number by yourself.)

原理图输入法制作的32位加法器。。。。。。。。(adder32)

对ad0809的控制代码( ad0809control)

扩频通信的Verilog工程，对从事无线通信的工程人员有参考作用。(Spread spectrum communication Verilog project, engaged in wireless communications engineering staff reference.)

在Qaurtus环境下用Verilog输入实现64QAM信号的发生，用MATLAB协助验证，观察了PN序列对应的星座图。(Simulating generation of 64QAM RF Signal in Quartus II IDE,identified with MATLAB,constellation gram displayed.)

Nios II 处理器上运行的 FIR 滤波器加速器

真是基于matlab的QPSK，格雷码，瑞利衰减信道，加性高斯白噪声仿真(Really based on matlab QPSK, Gray code, Rayleigh fading channel additive white Gaussian noise simulation)

使用verilog语言编写的colorbar输入，适合于用于图像采集系统的测试和验证用。