mooor状态机的VHDL程序，代码，状态机，关键是分析各个状态之间的切换...

2004 SNUG of systemverilog

it s vhdl program for decoder

说明：  串口操作源代码，本代码采用veilog hdl语言编写，并经过本人多次验证。(source code, the code used veilog HDL language, and after I repeatedly verified.)

EDK tutorial 1 ----------------

AD7606采集代码，用于verilog 驱动 AD7606 adc SPI 串口方式(AD7606 acquisition code, used for Verilog drive AD7606 ADC SPI serial mode)

这是QuarusII中文的用户指南！希望大家有用(This is a QuarusII Chinese User' s Guide! Hope that useful)

Browser modularization processing, browser modularization combing, browser modularization expansion

QUARTUSII 9.0 下的三级流水线中值滤波工程，vhdl源程序等。可用于fpga做图像预处理。(the three stage pipeline median filter project under QUARTUSII 9 , VHDL source program. which can be used by FPGA to do image preprocessing. )

黑金开发板对时钟信号的编写实验以及调试，相关代码如压缩包所示(CLOCK FPGA)

该程序描述并且模拟和实现了了一个摩尔有限状态机的功能和作用(The program describes the simulation and the function and role of a mole finite state machine)