vhdl programming from beginner level

RS编码器在fpga上的实现，用的modelsim开发环境(RS encoder in the realization of the fpga, development environment used in modelsim)

Counter written in VHDL.

VHDL Vendingmachine source

VHDL出租车计价器，包含所有代码及其仿真结果-VHDL Taximeter that contains all the code and the simulation results

说明：  RISC 5级流水线CPU，带HAZARD处理(RISC 5 pipeline CPU with HAZARD processing)

伽罗华域的乘法器的设计，使用有限域设计乘法器(Galois field multiplier design, the use of finite field multiplier design)

传感信号无线数字传输系统的设计与实现.kdh(err)

利用数字电路知识，进行二十四小时计时，并有闹钟与蜂鸣器功能-Knowledge of the use of digital circuits, the 24 hours time, and there is an alarm clock function and buzzer

CPU 5级流水线实现（加hazard处理与板级验证，板级验证带有按键消抖）(5-stage pipelined CPU (plus hazard dealing with board-level verification, board-level verification with key debounce))

加法器（使用verilog编写的）,虽然简单，但是这也是学习verilog最基础的东西！希望大家一起学习！-The accumulator (uses the verilog compilation), although it is simple, but this also is studies most foundation of the verilog! Hopes everybody studies together!