为了便于信号发射，提高信道利用率、发射功率效率以及改善通信质量，人们研制出各种通信信号的调制样式。尽管调制样式多种多样，但实质上调制不外乎用调制信号去控制载波的...

有用的数字钟设计文档，有秒表、闹钟等模块，希望对大家有用！(JUST LEARN FROM IT!!ENJOY!)

利用FPGA设计游戏设计，真人版超级玛丽，VGA显示(Using FPGA design game design, live-action version of Super Mario, VGA display)

PrimeTime Intro to STA -PrimeTime Intro to STA

Bayer 转RGB Verilog代码实现。。5*5 窗口。在工程中应用的(Bayer to RGB Verilog code implementation. 5*5 window. Applied in Engineering)

This Book description about LCD in Board DE2

64点的 FFT verilog,它是串行计算的，工作频率不到100M，计算速率很高，里面的层次很清晰。(64-point FFT verilog serial computing, the operating frequency of less than 100M, the calculated rate is high, the level inside is very clear.)

PID控制器的verilog实现，做闭环控制器的人可以参考(PID controller verilog implementation of closed-loop controller may make reference to)

本代码是实现了lwip协议栈,可以移植到其他类型的嵌如式操作系统上-This code is to achieve a lwIP protocol stack can be ported to other types of embedded operating systems such as the type

基于Xilinx Vertex2的可综合的2048x10位的读写可控制FIFO模块源代码，深度可控(Based on the Xilinx Vertex2 can be integrated 2048x10-bit read and write can control the FIFO module source code, the depth of controllable)

VHDLVERILOG语言实现的CARDBUS的IP源码,已经实现现场应用-CARDBUS IP CORE