7段数码显示译码器

verilog hdl 编写的64点fft代码，适合很多芯片(coded by verilog hdl that implement 64 point fft, suite to many core)

异步FIFO 设计源代码，内涵完整的verilog源代码和测试代码。-Source code for asyn_fifo using verilog language.

modelsim下的60进制计数器源码和测试激励文件(modelsim M counter 60 under the source file and test incentives)

5604FPGA驱动，能显示数字（5604里面为4个595）(5604 FPGA driver, able to display digital (5604 contains 4 595))

本人用verilog编写的UDP协议，经测试可用。(I am prepared to use verilog UDP protocol, the test is available.)

verilog code for counter four

自动售货机，与现实生活中的售货机功能类似，可以自动进行找零(Vending machines, vending machines and similar real life, there is a function to automatically calculate the price of goods)

vhdl 代码为基数 8 展位编码模块乘数与自适应延迟的高动态范围残留一些系统

关键词：清华大学计算机系 计算机组成原理大实验 多周期cpu工程源码，内含中断，串口，以及31个指令的实现，读写内存，控制器，ALU，寄存器，分频等模块，小作业什么的可以直接从里面摘抄，为学弟学妹造福(Keywords: Department of Computer Science Computer Composition Principle experimental multi-cycle the cpu Engineering source for the benefit of mentees)

this project is based on jk and t flip flop using vhdl.this is the 100 correct code,reference is taken from book digital electrionics written by anand kumar.please use quatrus to access this code.this code can be used for the final year project for engineering. Here dataflow techniques and behavioural techniques are used. -this project is based on jk and t flip flop using vhdl.this is the 100 correct code,reference is taken from book digital electrionics written by anand kumar.please use quatrus to access this code.this code can be used for the final year project for engineering. Here dataflow techniques and behavioural techniques are used.