7段数码显示译码器

异步的fifo,写时钟和读时钟相互独立，能够对数据进行缓存处理。希望对大家有用(Asynchronous fifo, write clock and the read clock independent of each other, capable of processing the data cache. I hope useful)

安富利SP605开发板ISE12.4版本的XBD文件，里面包括了开发板所有的接口，包括硬件和软件设计(Avnet SP605 development board ISE12.4 version XBD file, which includes the development board all interfaces, including hardware and software design)

CH4CH2CH1VHDL 数字电路参考书所有程序5-CH4CH2CH1VHDL digital circuit reference all proceedings 5

艾米电子的液晶1602的Verilog语言程序 (Amy e-LCD 1602 of the Verilog language program)

design and implementation of a format conversion system on the Altera NIOS board(QUARTUS) which reads an analogue input, converts it into digital data, and then does the reverse conversion back into analogue format. This will be done by taking an analogue an analogue input using SPI MCP3202 12-Bit A/D converter to generate the digital data stream and then the digital data will be used to generate an analogue output using Analog Devices 8-bit SPI AD7303 D/A converter.

说明：  等精度测频法，有需要的可以下载看看哟，word中包含的代码(Equal Precision Frequency Measurement Method)

基于FPGA的技术溢出研究程序，只是一个测试程序，大家可以下着用一下。-FPGA-based research process of technology spillovers is only a test procedure, we can next look forward to using.

这是一个最最常用的用vhdl写的状态机，几乎哪儿都用得到(a very good state machine)

基于FPGA的16QAM调制器设计与实现(Design and implementation of 16QAM modulator based on FPGA)

用VHDL实现60秒倒计时的功能 倒计时为0时蜂鸣器持续响起(Continued sounded to achieve 60 seconds of the countdown function with VHDL countdown to the 0:00 buzzer)