7段数码显示译码器

多进制数字频率调制(MFSK)系统VHDL程序-Multi-band digital frequency modulation (MFSK) system VHDL procedures

verilog语言写的一个四层电梯程序，有优先级的判断。(verilog language of a four-story elevator procedures to determine priority.)

基于Matlab的FPGA数字半带滤波器设计(Matlab-based FPGA digital half-band filter design)

高精度小数除法器设计与实现。 在FPGA开发板上实现小数除法器，输入输出信号N_in [15:0], D_in[15:0]，N_in[15:0]小于D_in，即被除数小于除数，输出商Q_out[15:0]中Q[15]一定为0，Q[14:0]为商的小数部分。输入和计算结果通过VGA显示。(Precision fractional divider design and implementation. In the FPGA development board fractional divider, input and output signals N_in [15: 0], D_in [15: 0], N_in [15: 0] less than D_in, ie the dividend is less than the divisor, quotient output Q_out [15: 0] in Q [15] necessarily 0, Q [14: 0] for the business of the fractional part. Input and calculation results display by VGA.)

acousting fingerprint enhancement

用VHDL编写简单的直流电机控制方法.供大家参考.-use VHDL to prepare a simple DC motor control methods. For your reference.

一组练习，关于VHDL的一些基础的知识和练习可以参考一些具体的问题-A group of exercises, on a number of VHDL-based knowledge and practice can refer to some specific questions

FPGA的仿真实例，Verilog代码编写，过程详尽，代码易懂。第四个文档-FPGA simulation examples, Verilog coding, the process in detail, code easy to understand. The fourth document

用Verilog实现汉明码编码，经测试可正确使用，代码简洁(Verilog with Hamming code encoding, the test can be used correctly, the code is simple)

使用nios2点亮一个led灯，使用软件quartus13.0，开发板de2-115(nios2 led quartus13.0 de2-115)