用VHDL langhantdma

对原信号进行拉格朗日插值运算，实现信号重采样(The original signal Lagrange interpolation operation, to achieve signal resampling)

对于32位寄存器前导零个数的计数，一个简单的程序(32 registers a leading zero number of counts, a simple procedure)

VHDL硬件描述语言与数字逻辑电路设计,学习VHDL的好资料-VHDL hardware description language and digital logic circuit design, VHDL learning good information

802.3an ldpc码编码、译码设计，使用VERILOG hdl语言编写，包括测试代码，(802.3an ldpc code encoding, decoding the design, use of language VERILOG hdl, including test code,)

DDS 产生正弦信号，OOK，AM三种波形。 使用xilinx FPGA VHDL(DDS. Resulting in sinusoidal signal, OOK, AM three waveforms. Using xilinx FPGA VHDL.)

用verilog写的4*4小键盘按键检测程序。本工程已经编译好。可以直接在Atera DE1 Fpga开发板上运行-Written using Verilog 4* 4 keypad keys detection procedures. The project has been compiled. Directly in the development of Atera DE1 Fpga board run

ARM教程,理解精辟，言简意赅，不错哦，欢迎大家看看(arm language )

计算多少次，把小砂轮安装数字传输比率是车轮的在一个更大完全旋转旋

verilog HDL经典的入门书籍，内容很详细，讲了许多实例，适合硬件描述语言初学者。(verilog HDL classic introductory book, the content is very detailed, spoke many instances, suitable hardware description language for beginners.)

针对Altera的DE2/ DE1交互板的音频核心的音频编解码器（编码器/解码器），并提供了音频输入和输出的接口。(The Audio Core interacts with the Audio CODEC (enCOder/DECoder) on the Altera DE2/DE1 Boards and provides an interface for audio input and output.)