用VHDL langhantdma

利用verilog写的PWM 程序，来实现产生呼吸灯的效果。(Using xerilog to generate breathing lamp)

按键控制数码管显示，从0到9显示，八位数码管(Button control digital tube display)

使用FPGA做的数码相册实验，用NIOS做了FAT32文件系统和JPEG图像解码,FPGA和SDRAM做了显示的缓存(Using FPGA to do the digital album experiment, using NIOS to do the FAT32 file system and JPEG image decoding, FPGA and SDRAM to do the display cache)

Verilog HDL 数字设计与综合，夏宇闻译。本书重点关注如何应用verilog语言进行数字电路和系统的设计和验证，不仅讲解语法，更从基本概念讲起，逐渐过渡到编程语言接口以及逻辑综合等高级主题。(The design and synthesis of Verilog HDL digital, Xia Wen translation. The book focused on how to apply the verilog language for the design and verification of digital circuits and systems, not only explain the grammar, the more I start from the basic concept, and a gradual transition to advanced topics such as programming language interface and logic synthesis.)

数字钟电路的实现，可以24小时计时，可调整时间！(Digital clock circuit implementation, a 24-hour timer, adjustable time!)

AMBA总线规范，能对从事嵌入式的同行们有一些帮助，让大家更好的理解ARM 结构和AMBA 体系(AMBA Specification)

本例介绍直接合成带阻滤波器的方法，n阶滤波器能实现n个传输零点(A direct synthesis technique of a new class of bandstop coupled resonator elliptic filters is presented. Two different coupling schemes, which both include source–load coupling are used. The first coupling and routing scheme is the standard folded structure used in implementing bandpass elliptic filters with transmission zeros using resonators.)

Package include hardware implementation of Lz77 algorithm

八阶巴特沃兹iir数字滤波器，四个二阶节，verilog代码实现，多路分时复用(batterworth，iir，8order，four second order section)

512阶高速FIR成型滤波器，四相位复用，树形加法和多级流水线结构。(512-order high-speed FIR shaping filter, four-phase re-use, tree addition and multi-stage pipeline structure.)