CORDIC算法的硬件实现 用的verilog语言

系数为4的扰码生成器，并每四位扰码产生一个触发串并转换的触发信号，可用于4b/5b编码的触发信号。verilog程序，带test程序-coefficient of the four scrambler generator, and every four scrambler have triggered a string conversion and the trigger signal can be used to trigger 4b/5b coding signal. Verilog procedures, with test procedures

yuv444 与yuv422相互转换verilog语言(yuv444 to yuv422)

获取主机CPU信息，VS2008编译通过，含详细说明(Get information on the host CPU, VS2008 compiler, containing detailed instructions)

说明：  Implementing SMPTE SDI Interfaces with UltraScale GTH Transceivers

freeDev数字应用开发板中的七段数码管的IP核的verilog实现-freeDev digital application development boards in the seven-segment digital tube of the IP core implementation of the verilog

PID控制器的verilog实现，做闭环控制器的人可以参考(PID controller verilog implementation of closed-loop controller may make reference to)

cordic 算法知道正弦和余弦值，求反正切，即角度。(The CORDIC algorithm knows sine and cosine values and asks for inverse tangent, that is, angle.)

verilog编写的SDRAM实验，有串口调试助手和相关资料！！！！！！！！！！！！！！！！！！！！！(Verilog prepared by the SDRAM experiment, a serial debugging assistant and related information!!!!!!!!!!!!!!!!!!!!!)

七段数码管显示的时钟程序VHDL代码 ISE编译环境(SEVEN seg VHDL ISE CLOCK)

说明：  quartusII 9.1，位同步提取电路，可以实现位同步时钟提取，其中包括分频器，和由D触发器以及与门组成的鉴相器模块。(Quartus II 9.1, bit synchronous extraction circuit, can realize bit synchronous clock extraction, including frequency divider, phase discriminator module composed of D trigger and and gate.)