简单 VHDL 波斯语

FPGA TW2867输入到ADV7171显示实验(FPGA TW2867 input to the ADV7171 display experiment)

任意数据发生器的源代码-arbitrary data source code generator

基于Verilog的图像采集、处理和存储程序，初学者参考，高手绕道。(Verilog-based image acquisition, processing and storage procedures, beginners reference, master bypass.)

verilog code for 3 bit sequence detector

freeDev数字应用开发板中的VGA控制器的IP核的verilog实现-freeDev digital application development board of the VGA controller IP core implementation of the verilog

Ethernet MAC-MII interface of Transmit

该程序实现的N位全减器，首先实现一位的减法器，之后实现N位全减器。-Program of the N-bit-wide reduction, the first realization of a subtraction for, after all N-reduction devices.

本程序是锁相环的仿真程序，具有接收端载波同步的功能。注释详尽，程序规范。发端的调制方式有单载波调制，BPSK调制，QPSK调制可供选择。程序中有星座图，锁相环的频差、相差图，以及解调后的基带波形。(This program is a phase-locked loop simulation program, the with carrier synchronization receiving end function. Notes detailed program specifications. The originator of the modulation scheme to choose a single carrier modulation, BPSK modulation, QPSK modulation. Program constellation diagram, the PLL frequency difference, a difference of FIG, and the demodulated baseband waveform.)

利用FPGA实现的脉宽测试技术,基于VHDL,测试误差为时钟周期-Use of FPGA technology to achieve the pulse-width test, based on VHDL, test error of clock cycles

通过正弦波和三角波的比较产生SPWM波形(Through the comparison of sine wave and triangle wave produces SPWM waveform)