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uart
说明: 串口通信通用模块,FPGA Verilog语言 ise,vivado环境(uart,FPGA Verilog, ise,vivado)
- 2020-06-22 07:20:01下载
- 积分:1
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fpga DDS ROM数据正弦波形正半周采样程序
fpga DDS ROM数据正弦波形正半周采样程序-fpga DDS ROM sinusoidal waveform is a half weeks of data sampling procedures
- 2022-03-09 21:09:04下载
- 积分:1
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加法器(使用verilog编写的),虽然简单,但是这也是学习verilog最基础的东西!希望大家一起学习!...
加法器(使用verilog编写的),虽然简单,但是这也是学习verilog最基础的东西!希望大家一起学习!-The accumulator (uses the verilog compilation), although it is simple, but this also is studies most foundation of the verilog! Hopes everybody studies together!
- 2023-07-08 05:35:13下载
- 积分:1
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电梯
利用verilog编写的电梯程序,实现基本的电梯运行功能(Elevator program written by Verilog)
- 2018-11-25 11:39:50下载
- 积分:1
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matlab_dspbuildings
matlab dsp building 工程欢迎下载(matlab dsp building )
- 2009-12-30 09:17:38下载
- 积分:1
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verilog ADPLL file with testbench
verilog ADPLL file with testbench
- 2022-04-20 22:45:21下载
- 积分:1
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FPGAVHDL
vhdl例程代码大全,包含流水灯,数码管,AD,DA转换等(Guinness vhdl code routines, including water lights, digital, AD, DA conversion)
- 2020-12-17 12:19:13下载
- 积分:1
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Complete-RAM
ram 64KB designed by haneesh in verilog
- 2011-07-15 00:57:01下载
- 积分:1
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McBSP_8bit_Asyn
基于FPGA的Mcbsp通信源码,经过项目实测检验(Mcbsp communication source code based on FPGA,Through the test of the project.)
- 2018-03-19 17:19:17下载
- 积分:1
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verilog-som
拿verilog编写的som(自适应神经网络算法),用于障碍物检测,基于FPGA可综合实验,已经在altera的cylcone上实现(Canal verilog prepared som (adaptive neural network algorithm) for obstacle detection. Based on FPGA synthesis experiments, in altera achieve the cylcone)
- 2020-07-09 20:38:55下载
- 积分:1