多功能数字时钟 功能齐全 vhdl fp

通信中常用的PN序列产生器的源代码全部打包(Communications commonly used in PN sequence generator, the source code of all packaged)

自动售货机的状态机实现 自动售货机的状态机实现(this is a automachine)

基于FPGA的AD和DA设计代码及文档(Design code and document of AD and DA based on FPGA)

基于FPGA开发的11阶半带升余弦FIR滤波器，用在阅读器基带滤波时的抽取滤波器使用，采用verilog语言实现。(Raised cosine FIR filter based FPGA development 11 order of half-band decimation filter used in reader baseband filtering, using verilog language implementation.)

偶数分频，包括验证程序，verilog实现，可综合-Even-numbered sub-frequency, including the verification process, verilog realize, can be integrated

用窗函数法设计一个线性相位FIR数字低通滤波器，用理想低通滤波器作为逼近滤波器，通带截止频率为0.2 ，阻带截止频率为0.4 ，阻带衰减不小于-40dB。(Window function method to design a linear phase FIR digital low-pass filter, as an ideal low-pass filter for approximation filter passband cutoff frequency of 0.2 stopband cutoff frequency of 0.4, the stop-band attenuation of less than-40dB.)

matlab代码，利用Farrow结构设计分数延时滤波器，滤波器阶数和个数可分别进行设置，利用最大最小准则近似。(Matlab code, using Farrow structure design fractional delay filter, filter order and number can be set separately, using the maximum and minimum criterion approximation.)

SDIO slave verilog code

ldpc编解码程序。有testbentch。-ldpc encoding and decoding process. There testbentch.

UART模块的VHDL语言设计(Design of VHDL language based on UART module)