吠陀乘数

包中包括, DW8051完整的Verilog HDL代码 两本手册: DesignWare Library DW8051 MacroCell, Datasheet DesignWare DW8051 MacroCell Databook 三篇51论文: 基于IP 核的PSTN 短消息终端SoC 软硬件协同设计 Embedded TCP/ IP Chip Based on DW8051 Core 以8051为核的SOC中的万年历的设计 (DW8051 is designed by synopsys, and its instruction cycle is 4 clock, which lead to about 3 times faster than Intel 8051 with the same oscillator frequency. I writed ram, rom, some other perpherals such as DES, RNG, and its testbench, and it worked all right!)

序列检测VHDL源代码，ATERA平台编译。详细的报表说明和模拟源代码。

EDA用maxplus2开发设计的简易数字钟，适合初学者，vhdL语言(EDA maxplus2 in development and design of simple digital clock, is suitable for beginners, vhdL language )

由忆阻器机制设计蕴含逻辑，内含testbench仿真文件(Design implied logic by memristor mechanism, including testbench simulation file)

这是一个在Quartus II软件中编写的vhdl程序。程序下载后可用蜂鸣器播放音乐 -This is a Quartus II software in the preparation of the VHDL program. After the buzzer can be used to download music player

说明：  模拟交通灯 verilog CPLD EPM1270 源代码(Simulation of traffic lights verilog CPLDEPM1270 source code)

the booth algorithm to implement the 32bits multiplication.-the booth algorithm to implement the 32bit "s multiplication.

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说明：  实现ARP、ICMP、UDP、TCP、IP和MAC全过程的传输，对TCP的连接、接收、发送、断开均经过测试，功能正常(Realize the transmission of ARP, ICMP, UDP, TCP, IP and MAC in the whole process, test the connection, reception, transmission and disconnection of TCP, and the function is normal)

fpga控制da产生幅值频率可调的正弦波程序(the fpga Control da produce the amplitude adjustable frequency sine wave program)