吠陀乘数

基于verilog hdl编写的FPGA正弦信号发生器，已测试。(FPGA sine signal generator)

verilog写的频率计程序的计数模块,-Verilog written procedures for counting frequency meter module,

说明：  this file describes the steps in building a fifo buffer module in verilog hdl and programming them on an fpga device

利用FPGA实现USB芯片CY7C68013与上位机的进行通信的系统，代码采用VHDL语言实现，利用状态机实现FPGA控制USB的数据传输，传输时序采用SLAVE FIFO实现

DDR控制器的VHDL源代码.采用FPGA实现DDR接口控制器,适用于Altera的FPGA,最高频率可到100M-DDR controller VHDL source code. Using FPGA DDR interface controller, applicable to Altera FPGA, the highest frequency available 100M

资源描述利用VHDL语言编写的浮点乘法器，可自定义浮点数位数，即乘数的参数化。具体为二进制有符号的浮点乘法器，二进制补码进行浮点运算。浮点数的表示是仿照IEEE格式，设置成自定义形式。

Content-addressable memory (CAM) is a special type of computer memory used in certain very-high-speed searching applications. It is also known as associative memory, associative storage, or associative array, although the last term is more often used for a programming data structure.

用于实现锁相光子计数技术的累加器，verilog语言(Accumulator achieve specific cases for accumulator lock detection of photon counting technique)

NiosII的C代码,包括网卡,lcd,usb,串口,按键.(NiosII C code, including network cards, lcd, usb, serial, key.)

这是一个HDB3的译码器，实现从HDB3双极性码到高低电平二值序列的转化-This is a decoder of the HDB3, HDB3 bipolar from high-low-level code to the conversion of binary sequences