-
EDAshiyan2s
通过上翻键和下翻键来设置方波信号正负脉冲宽度,利用一排流水灯来显示按键的次数,通过观察流水灯亮的盏数确定占空比(按一次上翻键亮一盏灯,流水灯全亮时占空比调到了最高或者是最低状态,按一次下翻键灭一盏灯,流水灯全灭时占空比调到了最低或者是最高状态)。(Duty cycle of LED lights and adjustable oscilloscope display code)
- 2015-01-06 21:10:09下载
- 积分:1
-
ECASP_tutorial.pdf.tar
adding custom ip EDK
- 2009-09-24 19:11:02下载
- 积分:1
-
这是使用VHDL语言编写的密码锁程序,供大家参考
这是使用VHDL语言编写的密码锁程序,供大家参考-This is the use of the VHDL code lock preparation procedures for reference
- 2023-04-25 08:05:03下载
- 积分:1
-
这是“状态机设计(讲稿)”,希望对正在学VHDL的同学有帮助,谢谢!...
这是“状态机设计(讲稿)”,希望对正在学VHDL的同学有帮助,谢谢!-This is the "state machine design (the script)", and I hope to learn VHDL is there to help the students, thank you!
- 2022-11-16 16:25:03下载
- 积分:1
-
通过实例的VHDL程序设计
VHDL programming by example
- 2022-03-19 05:46:52下载
- 积分:1
-
LMS
用verilog编写的lms算法。可实现自适应滤波功能(Lms algorithm written in verilog. Adaptive filtering can be achieved)
- 2021-05-15 11:30:02下载
- 积分:1
-
NN-using-FPGA
thesis about design and implementation neural network using FPGA
- 2013-12-29 16:23:52下载
- 积分:1
-
zuoye2
主要编写了一组二进制数据通过根升余弦滤波器后的波形,但并没有使用ISE内部的FIR滤波器内核,该程序相当于编写了一个根升余弦滤波器。(Mainly prepared a set of binary data through the root raised cosine filter waveform after, but did not use the ISE internal FIR filter kernel, the program is equivalent to the preparation of a root raised cosine filter.)
- 2013-09-18 15:24:13下载
- 积分:1
-
this project is based on half adder ,full adder,half subtractor and full subtrac...
this project is based on half adder ,full adder,half subtractor and full subtractor using vhdl.this is the 100 correct code,reference is taken from book digital electrionics written by anand kumar.please use quatrus to access this code.this code can be used for the final year project for engineering.
Here dataflow techniques and behavioural techniques are used.
-
this project is based on half adder ,full adder,half subtractor and full subtractor using vhdl.this is the 100 correct code,reference is taken from book digital electrionics written by anand kumar.please use quatrus to access this code.this code can be used for the final year project for engineering.
Here dataflow techniques and behavioural techniques are used.
- 2022-12-30 21:40:03下载
- 积分:1
-
vhdl testbentch 编写模板。非常实用
vhdl testbentch 编写模板。非常实用-vhdl testbentch prepared templates. Useful
- 2022-06-01 04:30:54下载
- 积分:1