本实施multilplier在vhdl.this源代码是有用的电脑学习…

文件名：ADC0809.vhd功能：基于VHDL语言，实现对ADC0809简单控制说明：ADC0809没有内部时钟，需外接10KHz~1290Hz的时钟号，这里由FPGA的系统时钟（50MHz）经256分频得到clk1（195KHz）作为ADC0809转换工作时钟。-File name: ADC0809.vhd features: Based on the VHDL language, easy to control implementation of the ADC0809 Description: ADC0809 internal clock does not need external 10KHz ~ 1290Hz clock number, here by the FPGA system clock (50MHz) frequency by 256 points to be clk1 (195KHz ) as the conversion ADC0809 clock job.

Control with DAC conversion

六十进制计数器，显示0到60.可以用数码管显示。(Six decimal counter 0-60 can use the digital display.)

这是用VHDL编写的译码程序,程序简单易懂-VHDL prepared decoding procedures that are simple to understand

DDR SDRAM控制器的VHDL代码已经测试-DDR SDRAM controller VHDL code

des加密算法的verilog语言的实现-des encryption algorithm to achieve the Verilog language

说明：  基于FPGA和弦！！！音乐芯片的设计与实现！！！(Design and implementation of FPGA chip based on the chord music)

带自适应波特率发生器UART实现，经过FPGA验证的！-UART baud rate generator with adaptive realization, after FPGA validation!

基于FPGA的调制，实现了QPSK调制，所用芯片为Artera的CycloneIIEp2C5T114C8-FPGA-based modulation, realize the QPSK modulation, the chip used for Artera

此VHDL语言程序可以控制液晶屏幕任意动画播放(The VHDL language program can control the LCD screen any animation)