-
log10(x)
Fixed-point base-2 logarithm (DW_log2)
// Computes the base-2 logarithm of a fixed point value in the
// range [1,2).
- 2014-09-11 19:58:10下载
- 积分:1
-
8BIT_CPU
一个8位的CPU设计,用verilog语言写的,希望有用(A CPU OF 8 BITS
)
- 2020-07-01 09:00:02下载
- 积分:1
-
SV-Combinational-Logic
system Verilog combinational logic
- 2017-01-24 18:50:29下载
- 积分:1
-
spi_test
基于fpga的spi通信测试 可与stm32进行spi通信测试(SPI communication test based on FPGA can test SPI communication with stm32)
- 2020-06-20 21:00:01下载
- 积分:1
-
ML605板子上的灯
ML605评估板上的流水灯,可以实现每隔0.16秒进行+1操作
#include
#include
#include
#include
#include
int main()
{
char a[] = "-100" ;
char b[] = "123" ;
int c ;
c = atoi( a ) + atoi( b ) ;
printf("c = %d
", c) ;
return 0;
- 2022-06-01 23:28:16下载
- 积分:1
-
595_8led
74hc595 driver 8 led
- 2013-03-28 21:10:33下载
- 积分:1
-
spi
VHDL实现SPI功能源代码
-- The SPI bus is a 3 wire bus that in effect links a serial shift
-- register between the "master" and the "slave". Typically both the
-- master and slave have an 8 bit shift register so the combined
-- register is 16 bits. When an SPI transfer takes place, the master and
-- slave shift their shift registers 8 bits and thus exchange their 8
-- bit register values.(SPI realize the functional VHDL source code The SPI bus is a 3 wire bus that in effect links a serial shift register between the )
- 2021-04-29 10:58:43下载
- 积分:1
-
VESA Timing
VESA CVT视频参数计算器,输入分辨率和刷新率即可得到需要参数。(VGA Timing Calculator)
- 2020-12-23 14:29:07下载
- 积分:1
-
cla - Copy
说明: ADDER USING VERILOG ADDER WITH VERILOG VERILOG ADDER
- 2019-03-19 01:35:37下载
- 积分:1
-
ffirr_166i
fir低通滤波器 用于dspbuilder pll:25nss data 400khz sin 10.8khz 已通过测试。
(fir low pass filter for dspbuilder pll: 25nss data 400khz sin 10.8khz has been tested.)
- 2012-06-10 17:54:50下载
- 积分:1