ROM的4位的话。

Fixed-point base-2 logarithm (DW_log2) // Computes the base-2 logarithm of a fixed point value in the // range [1,2).

一个8位的CPU设计，用verilog语言写的，希望有用(A CPU OF 8 BITS )

system Verilog combinational logic

基于fpga的spi通信测试 可与stm32进行spi通信测试(SPI communication test based on FPGA can test SPI communication with stm32)

ML605评估板上的流水灯，可以实现每隔0.16秒进行+1操作 #include #include #include #include #include int main() {   char a[] = "-100" ;   char b[] = "123" ;   int c ;   c = atoi( a ) + atoi( b ) ;   printf("c = %d ", c) ;   return 0;

74hc595 driver 8 led

VHDL实现SPI功能源代码 -- The SPI bus is a 3 wire bus that in effect links a serial shift -- register between the "master" and the "slave". Typically both the -- master and slave have an 8 bit shift register so the combined -- register is 16 bits. When an SPI transfer takes place, the master and -- slave shift their shift registers 8 bits and thus exchange their 8 -- bit register values.(SPI realize the functional VHDL source code The SPI bus is a 3 wire bus that in effect links a serial shift register between the )

VESA CVT视频参数计算器，输入分辨率和刷新率即可得到需要参数。(VGA Timing Calculator)

说明：  ADDER USING VERILOG ADDER WITH VERILOG VERILOG ADDER

fir低通滤波器 用于dspbuilder pll：25nss data 400khz sin 10.8khz 已通过测试。 (fir low pass filter for dspbuilder pll: 25nss data 400khz sin 10.8khz has been tested.)