ROM的4位的话。

16次迭代的CORDIC算法，精度很高，可应用于计算反正切值(16 iterations of the CORDIC algorithm, high accuracy, can be applied to calculate arctangent)

vhdl code fpga for lcd 2*16

关于USB开发的verilog开发程序，非常的全面，学习FPGA开发时用得着。(About USB development verilog development process, very comprehensive, learning FPGA development time worthwhile.)

基于vhdl编写的贪吃蛇游戏，课程设计必备(Based on the VHDL language of the snake game, curriculum design essential)

简易函数发生器，能产生正弦波，三角波，梯形波，方波，并且可调频率和幅度值。(Simple function generator can produce sine, triangle wave, trapezoidal wave, square wave, and the adjustable frequency and amplitude values.)

这是一个FIFO_Buffer的verilog代码.(This is a FIFO_Buffer the Verilog code.)

说明：  lvds_rx IP核硬件设计代码，使用时注意LVSD_RX模块的延时参数的设置，3.5倍时钟相位的设置(Lvds IP core hardware design code, when using the attention LVSD module delay parameter settings, 3.5 times the clock phase settings)

lap of altera . it s basic about verilog

Program for Code Gerneration

Multisim11下8051跑马灯仿真。(The 8051 Marquee under Multisim11 simulation.)