LCD的Spartan3E FPGA VI

自己编的一个分频器的程序模版 虽然原理很简单，经过多次实践很实用 被多次用在其它的程序中-own series of the dividers of a procedure template Although very simple principle, after repeated practice by many very practical use in other proceedings, and,

说明：  用VERILOG编写的一个可以实现VGA显示的程序.....(Prepared using a VERILOG VGA display program can .....)

改进的DCT算法设计，veriloghdl实现-Improved DCT algorithm design, veriloghdl realize

DDS中的正余弦生成，初始相位相差90度，可自行改变输出频率(Cosine generation of DDS, the initial phase difference of 90 degrees, the output frequency can be changed on their own)

设计一个8位有符号数字平方器。平方器将接收操作数B，一个8位有符号数。新兴市场；

出租车计费，器设计一个出租车自动计费器，计费包括起步价、行车里程计费、停止和暂停不计费三部分。现场模拟汽车的启动、停止、暂停和换挡状态。分别用四位数码管显示金额和里程，各有两位小数，行程 3公里内，起步费为6元，超过3公里，以每公里1.3元计费(Car repair billing device)

This is a bridge IP core to interface the Tensilica PIF bus protocol with the OpenCores WishBone. It currently supports single-cycle as well as burst transfer operations. The core has been tested in a master-PIF slave-WB configuration.-This is is a bridge IP core to interface the Tensilica PIF bus protocol with the OpenCores WishBone. It currently supports single-cycle as well as burst transfer operations. The core has been tested in a master-PIF slave-WB configuration.

本verilog代码通过IIC总线实现了对 PCF8591AD、DA转换芯片的控制。适用于FPGA，亲测可用。(this is used for FPGA to control PCF8591(AD/DA) chip by verilog.)

AHB_Lite 通信协议的FPGA Verilog 设计(AHB_Lite communication protocol Verilog design in FPGA)

verilog实现UART收发功能，硬件平台为spartan 6，软件平台为ise14.7(verilog implement UART rx and tx function)