北邮数电实验代码

this describes building spi block on verilog hdl and programming them on an fpga device

基于Max+Plus II和VHDL的电子密码锁设计(Based on Max+ Plus II electronic lock and VHDL design)

VHDL写时钟，分频模块什么，实现计时。定点报时，定点闹钟，显示年月日。(verilog HDL)

crazy bingo 韩彬将要出版的新书《FPGA设计技巧与案例开发详解》中的所有配套例程源码，主要涉及视频开发方向。(All the supporting source code routines crazy bingo Han Bin will be published book FPGA design techniques and case development explain in the video, mainly relates to the development direction of.)

these files are written in verilog but i am uploading in text format

说明：  此代码是由FPGA产生SPWM波的代码，简单易懂(use FPGA to generate SPWM)

说明：  LTE is an abbreviation for Long Term Evolution.

Material to learn how to use system verilog and how to write testbenches for verification.

光纤发送接收模块，verilog编写，主要用于光纤的发送和接收，波长1310nm(Fiber optic transmitter receiver module, verilog written primarily for transmitting and receiving the optical fiber, wavelength 1310nm)

matlab code for communication