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DAC_sinewave_timer_int
8051 1Khz sine wave generator. make use of DAC0808 and timer 0 interrupt. Also single led is blinked continuously.
- 2011-12-12 13:19:08下载
- 积分:1
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04432909
基于FPGA实现的神经网络算法ANN。针对手势识别,不错的参考文章。(Hand Postures Recognition System Using Artificial Neural Networks
Implemented in FPGA)
- 2015-06-25 06:34:19下载
- 积分:1
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This document gives the code for programming a CC2500 transceiver using Altera S...
This document gives the code for programming a CC2500 transceiver using Altera Stratix FPGA. The FPGA and CC2500 are connected through SPI mode with the FPGA as the master and CC2500 as the slave.
- 2022-02-26 15:59:21下载
- 积分:1
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modulation-and-demodulation
通过verilog语言实现各种基本信号的调制解调过程,包括2psk,qpsk,ppm(Realize the modulation and demodulation process of various basic signals through verilog language, including 2psk, qpsk, ppm)
- 2018-04-26 21:52:04下载
- 积分:1
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国外经典verilog代码,很适合初学者,其中的有些概念对老手也可以考虑下...
国外经典verilog代码,很适合初学者,其中的有些概念对老手也可以考虑下-Foreign classic Verilog code, it is suitable for beginners, of which some of the concept of a veteran may also want to consider under the
- 2022-02-24 14:20:37下载
- 积分:1
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UART
字长可以简单调整,即可实现任意字长UART通讯(The word length can be simply adjusted to achieve any word length UART communication.)
- 2018-07-09 22:06:02下载
- 积分:1
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QuartusII
基于QuartusII环境下以模块化的形式做成的视频复合同步信号。-QuartusII-based environment to create the form of modular composite video sync signal.
- 2022-03-03 23:44:07下载
- 积分:1
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pc_cfr_test_v3_1c
一个关于降低现代通信系统中高峰均比信号的matlab算法,对于研究数字预失真基于FPGA实现的有一定作用!(A modern communication system on the lower than the peak signal matlab algorithm for FPGA-based study of digital pre-distortion to achieve a certain effect!
)
- 2011-07-07 22:01:17下载
- 积分:1
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Array-multiplier
Array muiltiplier verilog code.. 4 bit two inputs with 8 bit outputs
- 2015-02-21 12:59:12下载
- 积分:1
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Chapter10
第十章的代码。
本书通过100多个模块实例,详细地讲解了Verilog HDL程序设计语言,全书共分13章,内容涉及VerilogHDL语言基本概念、建模、同步设计、异步设计、功能验证等,实例包括各种加法器/计数器、乘法器/除法器、编码器/译码器、状态机、SPIMaster Controller、I2C Master controller、CAN ProtocolController、Memory模块、JPEG图像压缩模块、加密模块、ATA控制器、8位RISC-CPU等及各个实例模块相应的Testbench,所举实例具有很强的实用性和代表性,每个实例均给出了介绍、功能分析、程序代码和结果演示(Chapter X code. This book by more than 100 module instance, explain in detail the Verilog HDL programming language, the book is divided into 13 chapters, covering basic concepts VerilogHDL languages, modeling, synchronous design, asynchronous design, functional verification, etc. Examples include a variety of additions device/counters, multipliers/dividers, encoders/decoders, state machines, SPIMaster Controller, I2C Master controller, CAN ProtocolController, Memory modules, JPEG image compression module, encryption module, ATA controller, 8-bit RISC-CPU etc. and the various instances of the corresponding module Testbench, The examples are highly practical and representation, each instance of it all gives the introduction, functional analysis, program code and the results demonstrate)
- 2009-11-17 13:52:32下载
- 积分:1