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北邮数电实验代码

于 2022-01-29 发布 文件大小:162.60 kB
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实验一:QuartusⅡ原理图输入法设计与实现一:实验要求    ①:用逻辑门设计实现一个半加器,仿真验证其功能,并生成新         的半加器图形模块单元。    ②:用实验一生成的半加器模块和逻辑门设计实现一个全加器,仿真验证其功能,并下载到实验板测试,要求用拨码开关设定输入信号,发光二极管显示输出信号。    ③:用3线—8线译码器和逻辑门设计实现函数F,仿真验证其功能,下载到实验板测试。要求用拨码开关 设定输入信号,发光二极管显示输出信号。二:报告内容

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