异步FIFO verilog源码及testbench

可以实现DDC各个模块的功能，如内插、抽取、FIR滤波等功能(DDC can realize the function of each module, such as interpolation, extraction, FIR filtering)

利用VHDL编写的电子琴发生器，以简单的演奏电路论文(Electronic organ prepared using VHDL generator to perform a simple circuit Papers)

是51单片机常用头文件定义，直接调用就可以，包括：1602液晶，12864液晶，5110屏，I2C,UART,精确延时函数，PWM调速，DS1302，DS18B20,,,,,,,(51 microcontroller used header file defines direct call can include: 1602 LCD, 12864 LCD, 5110 screen, I2C, UART, precision delay function PWM speed control, DS1302, DS18B20,,,,,)

xilink DPD V6.0 IP Core design example

说明：  自己写的CRC的Verilog代码，在网上收集的crc相关的代码以及crc的matlab仿真代码(The CRC Verilog code written by myself, CRC related codes collected on the Internet and CRC matlab simulation code)

Encryption has become a part and parcel of our lives and we have accepted the fact that data is going to encrypted and decrypted at various stages. However, there is not a single encryption algorithm followed everywhere. There are a number of algorithms existing, and I feel there is a need to understand how they work. So this text explains a number of popular encryption algorithms and makes you look at them as mathematical formulas.

FPGA编写环境，具有仿真容易，软件内存小的特点(FPGA authoring environment, with easy simulation software features small memory)

design and implement a digital system on the Altera NIOS board which will read an analogue input using MicroChip’s SPI MCP3202 12-Bit A/D converter. The 8 most significant bits of the converted data will be displayed on two seven segments of the NIOS development board. The sampling frequency is 20kHZ. Use a potentiometer.(design and implement a digital system on the Altera NIOS board which will read an analogue input using MicroChip' s SPI MCP3202 12-Bit A/D converter. The 8 most significant bits of the converted data will be displayed on two seven segments of the NIOS development board . The sampling frequency is 20kHZ. Use a potentiometer.)

说明：  介绍了FPGA的使用以及modelsim联合synplify工具的使用方法(This paper introduces the use of FPGA and the use of Modelsim joint Synplify tool)

VHDL上百实例 包括 ADDER LATCH FIPPER AND ETC..(VHDL hundreds of examples, including ADDER LATCH FIPPER AND ETC ..)