VHDL_COUNTING 时间使用按钮 (Đếm giờ phút giây sử dụng nút nhấn)

用vhdl设计实现的多功能电子钟，可有日历，闹钟，修改等多种功能-With VHDL Design and Implementation of the multi-functional electronic bell, can have a calendar, alarm clock, to amend a variety of functions such as

说明：  简单流水线CPU，使用 verilog实现，实现一条指令的整个流程(Implementation of Simple Pipeline CPU Verilog)

uart16550 ip core 通用异步收发器vhdl源代码-uart16550 ip core UART VHDL source code

rgmii接口通讯方式，用于FPGA以太网口开发(Rgmii interface communication mode)

fpga实验板上16*16点阵显示汉字的程序-翻译结果fpga实验板上16*16点阵显示汉字的程序(Experimental fpga board 16* 16 dot matrix display Chinese program- translation results fpga experimental board 16* 16 dot matrix display Chinese characters in the program)

LIBRARY IEEE USE IEEE.STD_LOGIC_1164.ALL USE IEEE.STD_LOGIC_ARITH.ALL USE IEEE.STD_LOGIC_UNSIGNED.ALL

4 seg display, button debouncer, and controller for parking meter

vhdl寄存/计数器设计-VHDL Storage/counter design

I am in need of some codes of HDL

异步fifo实现，通过双口ram实现异步fifo(Asynchronous FIFO implementation, through dual port RAM to achieve asynchronous FIFO)