VHDL_COUNTING 时间使用按钮 (Đếm giờ phút giây sử dụng nút nhấn)

用VERILOG实现一个被除数为8位、除数为4位的高效除法器(With VERILOG implement a dividend for the 8-bit, 4-bit effective divisor divider)

实现拟想要的音乐，基于at89s51单片机的电子琴设计！(To achieve the desired music to be based at89s51 keyboard microcontroller design!)

有关gal器件的编程入门，以及常见逻辑门、计数器VHDL程序(For gal device programming entry, as well as common logic gates, counters VHDL program)

设计含异步清零和同步时钟使能的加法计数器-Clear design with asynchronous and synchronous clock so that the adder counter

ADI ad9361 vivado 下源代码(ADI ad9361 vivado source code)

自己编的VGA彩条信号发生器verilog ise环境-Own the VGA color signal generator verilog ise Environment

简单流水线CPU，使用 verilog实现，实现一条指令的整个流程(Implementation of Simple Pipeline CPU Verilog)

GPU编程的经典之作,值得一读。 GPU运算效率比CPU高出一截，学习GPU编程会大有裨益(a book for GPU_Programming)

数控分频器的设计 数控分频器的功能就是当在输入端给定不同输入数据时，将对输入的时钟信号有不同的分频比，例3的数控分频器就是用计数值可并行预置的加法计数器设计完成的，方法是将计数溢出位与预置数加载输入信号相接即可。(NC NC divider divider design of its function is when the input given different input data, input the clock signal will have different frequency than, for example 3 is to use the NC prescaler count preset value of the adder parallel counter design is completed, the method is to count the number of overflow bit with preset load to the input signal phase.)

本人编写的FPGA光电编码器输入模块,没有实验,但仿真基本实现,希望有参考价值.(FPGA optical encoder input module, there is no experimental, but simulation technology, hope to have reference value.)