VHDL_COUNTING 时间使用按钮 (Đếm giờ phút giây sử dụng nút nhấn)

迫零-串行干扰删除检测的程序，包括16QAM和QPSK(Zero forcing- Interference Cancellation detection procedures, including 16QAM and QPSK)

说明：  Verilog简易教程，或者说是讲义，清晰易懂，适合初学者入门使用(Layman' s Guide to Verilog, or a lecture, legible entry to use for beginners)

说明：  BUS documentation and map reffereces

verilog实现RTC功能，可直接用于芯片开发中。(verilog achieve RTC function can be directly used for chip development.)

基于CPLD的交通灯控制，完成交通灯的功能，校错能力(CPLD-based control of traffic lights, traffic lights to complete the function, the school was wrong capacity)

将BT656数据流转换成RGB图像格式的数据(Converting BT656 data stream into RGB image format)

说明：  quartusii软件仿真实验代码 双二选一(quartusii software simulation code for a pair of two elections)

基于FPGA的uart控制器，波特率可选，VHDL编程，Quartusii 6.0 平台，vhdl语言编程-FPGA-based UART controller, an optional baud rate, VHDL programming, Quartusii 6.0 platform, vhdl language programming

由乘法器组成 单边带信号产生的 仿真源代码 msm (Composed of single sideband signal by the multiplier generated simulation source code msm)

说明：  用verilog编辑的中值滤波器！语言旁表有注释方便理解！(Using Verilog editor median filter! Language beside the table annotated to facilitate understanding!)