多周期cpu实现 计算机组成

sram 6bit仿真模型，verilog编写(sram 6bit simulation model, verilog prepared)

实现AHB转SRAM接口实现，支持猝发，零等待延迟(Implementation of AHB to SRAM Interface)

基于UVM的CRC电路验证程序，包含基本的CRC电路模块，testbench，给出了UVM的实现

Verilog code of SPI configurator for DAC AD7394 and AD7395

基于verilog的出租车付费系统 带验证模块

Verilog实现DDS线性调频，Verilog实现DDS线性调频(Verilog implementation of DDS linear FM，Verilog implementation of DDS linear FM)

writing testbench in system verilog

说明：  FPGA实现PLL锁相环，输出不同频率的时钟控制信号。(FPGA realizes PLL and outputs clock control signals of different frequencies.)

本文分析了当前国内外出租车计费系统的基本组成和工作原理及主要的两种设计方式:基于单片机的设计方式和基于FPGA的设计方式；并对这两种实现方式的优点和缺点进行分析，比较后确定本系统的方案：基于FPGA的出租车计费系统的设计。(This paper analyzes the current taxi charging system at home and abroad, working principle and basic components of two major design approach: the design methods based on single chip FPGA-based design approach and the two implementations to analyze the strengths and weaknesses, After comparing the program to determine the system: FPGA-based taxi billing system.)

多周期CPU设计所有模块全部代码，ISE工具环境下，经验证成功实现