ADPLL 行为模型

说明：   基于VHDL语言数字秒表设计,在FPGA实验平台下开发(Digital stopwatch design based on VHDL, FPGA experimental platform under development)

QPSK调制的载波频偏估计，是一个可以调用的函数。接收端进行了一系列的处理。经典的Kay法(QPSK-carrier frequence offset estimation_ kay )

完整的verilog编写的源代码，根据实际所用的器件，修改相关参数，就可实现VGA的驱动。

project proposal of verilog language that is gud for beginners

说明：  Verilog实现按键消抖，工程，已下板验证通过。(Verilog achieves keystroke jitter elimination. The project has been validated on the lower board.)

说明：  FPGA程序的top.v文件，主要实现DDS信号发生器功能，通过定时器，可简单实现输出幅值无极跳变(FPGA procedures top.v documents, the main function of DDS signal generator, through the timer can be simple to achieve the output amplitude wuji hopping)

本代码是基于可编程门阵列flield视频图形阵列实现。该代码是使用Verilog

fpga hardware hevc implementation

从bt656数据流中提取出同步信号, 适合于搞fpga/cpld开发调式(bt656 internel sync to extern sync singal， bt656 internel sync to extern sync singal)

XAPP585 serdes_1_to_7 and serdes_7_to_1 data