这是最后一个，处理器内部ROM，如有需要，大家就顶

fault minimization using genetic algorithm

depends on irda transmitter recever

least mean square algo implemented on verilog

ps2接口的工程实现，顶层为原理图，便于理解-ps2 interface engineering implementation, the top-level schematic diagram for easy understanding of

ALTERA NIOS处理器实验，QUARTUS下用VHDL编译成处理器，然后NIOS　SHELL下C 语言运行。实验SRAM和DMA调度-Altera NIOS processor experiments QUARTUS using VHDL compiler into processor, then NIOS SHELL C language runtime. Experimental SRAM and DMA Scheduling

HDMI做为视频输出输入接口已经广泛使用很长时间，主要通过TMDS差分编码传输。本实验通过在HDMI屏幕上显示彩条和输入输出环通实验，来练习视频的时序和视频颜色的表示，为后面视频处理实验做个基础。(HDMI as video output input interface has been widely used for a long time, mainly through TMDS differential coding transmission. In this experiment, by displaying color bars and input/output loop experiments on HDMI screen, video timing sequence and video color representation are practiced to lay a foundation for video processing experiments later)

用VERILOG HDL实现的任意 频率分频器源代码，是一个通用的程序-With VERILOG HDL realize arbitrary frequency divider source code, is a generic procedure

定时器加数码管显示源码，以及test bench测试模块源码，经modelsim仿真结果正确(Timer plus digital display source code, and test bench test module source code, by modelsim simulation results are correct)

Verilog的135个经典设计实例.使你工作使用学习中，会有很大帮助，各种典型案例(135 classic Verilog design examples. Make your work with the study, will be of great help, of various typical cases )

次源码实现一个扩频接收机系统，用VHDL语言编写，并且有完整得测试程序-Second source to achieve a spread spectrum receiver system, using VHDL language, and have a complete test procedure was