PWM for control of motors

基于ARM的DDS信号发生器设计，可以产生各种信号的波形，生成所需要的信号，可供实验用(DDS signal generator based on ARM, can produce a variety of signal waveform can be used for experiment)

UART RS232 IPCORE for sopc builder -RS232 UART IPCORE for sopc builder

用状态机实现一序列检测器，即检测到串行码{1110010}后，检测器输出1，否则输出0； -State machine used to achieve one sequence detector, which detects the serial code (1110010), the detector output 1, otherwise output 0

《Altera FPGA_CPLD设计 高级篇》详细介绍FPGA应用于高级特性，LogicLock设计，时序约束，设计优化，高级工具及系统级设计技术，是深入学习FPGA的重要材料(" Altera FPGA_CPLD advanced part design" details FPGA used in advanced features, LogicLock design, timing constraints, design optimization, system-level design tools and advanced technology, in-depth study is an important material for FPGA)

DRD3在Xlinix平台上的设计教程以及仿真(DRD3 design tutorial and Simulation on Xlinix platform)

基于Xilinx FPGA实现PS2键盘鼠标接口。版本1.0-Based on Xilinx FPGA realize PS2 keyboard and mouse interface. Version 1.0

说明：  basys3的数字钟，可以显示00.00-59.59(Digital clock of basys3,It can display 00.00-59.59)

对视频编解码芯片ADV7181进行合理的配置，使其输出符合ITUR656标准的视频流-Of the ADV7181 video decoder chip for a reasonable configuration, so that the output in line with the standard video streaming ITUR656

ISA总线资料《ISA System Architecture》(ISA System Architecture)

8bit/10bit编码Verilog实现(8bit/10bit Verilog Code)