Verilog串口UART程序

有符号16位乘法器。经典booth编码。拓扑结构为wallance树。加法器类型是进位选择加法器。(Number system: 2 s complement Multiplicand length: 16 Multiplier length: 16 Partial product generation: PPG with Radix-4 modified Booth recoding Partial product accumulation: Wallace tree Final stage addition: Carry select adder )

利用FPGA实现与powerpc的localbus数据接口代码。用verilog实现(localbus interface with PowerPC using Verilog)

完成APB slave 的单次寄存器读写控制，相同时终域完成，简单操作

本文阐述了设计的 4 位携带看前方 adder.this 加法器是比较会波及进位加法器的高速度。

A controller for DDR2 on FPGA with vhdl, content testbench, model and textfile-generation/data-detection using python.

说明：  Digital pre-distortion (DPD) is an advanced digital signal-processing technique that mitigates the effects of power amplifier (PA) nonlinearity in wireless transmitters. DPD plays a key role in providing efficient radio digital front-end (DFE) solutions for 3G/4G basestations and beyond. Modern FPGAs are a promising target platform for the implementation of flexible wireless DFE solutions, including DPD.

展位的乘法算法是将在两个的补充符号两个符号二进制数字相乘的乘法算法。展位的算法可以通过反复添加 （与普通的无符号二进制加法） 两个预设值 A 和 S P，然后对体育执行算术右移产品之一让 m 和 r 是被乘数和乘数，分别;让 x 和 y 代表中 m 和 r 位的数目。

液晶ST7565P_12864驱动，实现打点成图。(LCD ST7565P_12864 drive, dot mapping.)

用于数字积分器的设计，主要涉及VHDL、Verilog等FPGA编程语言。(Design of Digital Integrator)

说明：  s29gl256s nor flash 源代码(s29gl256s device source code)