Verilog串口UART程序

数字钟：实验中用到的小程序，用于万年历中的模块(Digital clock: a small program used in the experiment, the modules for calendar)

说明：  SJA1000的ip核和相关测试脚本,OPENCORES 下载(SJA1000 IP downloads from opencores)

这个verilong代码实现的功能是radar processing的功能。(This verilong code function is radar processing functions.)

用verilog 语言编译16QAM调制(a great complied code of 16QAM modulation for OFDM)

project proposal of verilog language that is gud for beginners

本程序为捷变频信号的verilog源代码设计实现的仿真，并含有相应捷变频信号在MATLAB仿真的结果(The procedure for the Czech Republic converted signal verilog source code design and implementation of the simulation, and the Czech Republic frequency signal containing the corresponding simulation results in MATLAB)

Control with DAC conversion

基于无源蜂鸣器和矩阵按键的电子琴系统设计(design of Electronic Piano System Based on Passive Buzzer and Matrix Key)

说明：  设计一个挂载在 APB 总线上的计数器，按照 APB 的时序给计数器赋值，主 机通过地址对计数器进行配置，通过数据输入端口给计数器设置计数器最大值， 并通过数据输出端口输出计数器的计数值。该设计还设置了一个计数完成信号， 当计数器满足模式配置后的计数要求时，会将该信号拉高(A counter mounted on the APB bus is designed. The counter is assigned according to the sequence of APB The computer configures the counter through the address and sets the maximum value of the counter through the data input port, And output the count value of the counter through the data output port. The design also sets a count completion signal, When the counter meets the counting requirements after the mode configuration, the signal will be pulled high)

Ethernet MAC-MII interface of Transmit