展位的乘数的 8 位 Verilog 代码

FPGA设计的四种常用思想与技巧，包括乒乓操作、串并转换、流水线操作、数据接口同步化(FPGA design of the four common ideas and techniques, including the operation of ping-pong, SERDES, pipelining, synchronization of data interface)

morris mano basic vhdl code in ise

手把手教你学FPGA 仿真篇,简单实用。(Hand in hand teach you to learn FPGA simulation, simple and practical.)

对锁相环路的仿真，二阶环的仿真与分析都可以通过这个文件来到完成(Simulation of PLL, second-order loop simulation and analysis can be completed by the adoption of the document came)

高速串行设计FPGA-GTX IP设置生成drp模块，可动态配置速率2.4Gbps，1.2Gbps，0.6Gbps，自适应链接(High-speed serial design FPGA-GTX IP setting generation drp module, dynamically configurable rate 2.4Gbps, 1.2Gbps, 0.6Gbps, adaptive link)

说明：  spartan6学习资料，官方资料，用户手册，包括5个主要文件(Spartan 6 Learning Materials, Official Materials)

中山大学计组实验--单周期CPU设计，实现12条指令，基于xilinx ISE 14.4 测试通过

verilog jtag源码及原理，还有debug模块。边界扫描等(verilog jtag source and principle, as well as debug module. Boundary-Scan, etc.)

Complete Successive approximation Analog to digital converter along with the source code

VERILOG HDL pid算法 带仿真验证(pid by verilog HDL)