Nexys 3 的分频器

圖形介面乘法器,也可自行使用verilog去改(Graphical interface multiplier, also free to use verilog go and change)

System Verilog decodificator. Enters a value(binary), drops hundreds, tens and units in BCD

华为文档《硬件描述语言Verilog基础》-目录 原来搞VHDL，刚刚开始学Verilog。觉得这个入门的提纲不错，共享一下。 (Huawei Documents " basic Verilog Hardware Description Language" - the original directory engage in VHDL, just beginning to learn Verilog. Feel that the entry of the outline of a good, share some.)

程序用VHDL实现： 频率合成，DDS 主要调用LPM-procedures using VHDL : frequency synthesis, DDS major call LPM

VHDL handbook is very nice and suitable guide to HVDL language

这是一个有关单周期CPU设计的一个参考，里面顶层模块已经写好，而其他模块的内容则是以注释的形式存在，如果要跑这个代码的话，把include的那些代码注释掉然后再将各个模块被注释的代码取消注释即可。( 翻译关闭即时翻译 英语 中文 德语 检测语言 中文(简体) 英语 日语 这是一个有关单周期CPU设计的一个参考，里面顶层模块已经写好，而其他模块的内容则是以注释的形式存在，如果要跑这个代码的话，把include的那些代码注释掉然后再将各个模块被注释的代码取消注释即可。 This is a reference about a single cycle CPU design, top-level module which has been written, and the contents of the other modules exist in the form of comments, if run this code, those codes include the commented out and then each module is uncommented to commented code.)

本源码为Nios II的开发示例,主要演示基于Nios II的uCOS的移植。开发环境QuartusII。 本示例十分经典，对基于SOPC开发的FPGA初学者有很大帮助。-The source code for the Nios II development of examples, mainly based on the Nios II shows the uCOS transplant. Development environment QuartusII. This example is very classic, FPGA-based SOPC development of great help for beginners.

该代码为VHDL语言描述的AD579 SPI通讯程序，包括一些代码注解。(Thisis a SPI communication promgram of AD5791 designed with VHDL which compared with some discreption.)

verilog开发FPGA，实现RS485串口通信(RS485 driver for FPGA )

用以VGA显示的小程序，很实用，挺有价值的(VGA display for a small program, very practical, quite valuable)