用VHDL写的运动计时表程序，用Modelsim仿真已经通过，帖出来与大家分享。...

verilog设计点滴经验，对fpga设计人员很有好处-Experience in verilog design

FPGA上用verilog写的SPWM控制程序，完美运行！自由调试，毕设内容，十分宝贵(The SPWM control program by verilog FPGA perfect run! Free commissioning, Bi-based content, invaluable)

8位crc的verilog设计 通过仿真综合验证并已应用在工程里面 (verilog of 8bit error checkout )

CPLD对mcbsp的收发操作，占用资源很少(CPLD to mcbsp transceiver operation, small footprint)

说明：  可以获取各种字符，并在数码管显示出来，非常的靠谱且稳定(Various characters can be acquired and displayed on the digital tube.)

Ethernet 10GE MAC 以太网10G的MAC Verilog代码实现(Ethernet 10GE MAC)

本代码可以用于产生正余弦信号波形，利用FPGA内部的ROM放置一个正余弦采样点的数据表格，通过循环取址的方法，实现波形连续输出。-This code can be used to generate positive cosine signal waveforms, using FPGA" s internal ROM to place a sampling point is the cosine of the data tables, the circulation method of taking the site to achieve a continuous output waveform.

基于FPGA 的12864液晶显示汉字，用verilog编写的。(12864 liquid crystal display Chinese characters based on FPGA, written in verilog.)

verilog HDL编写的出租车计费系统-verilog HDL prepared Taxi Accounting System

IP 核的接口（The Avalon® Streaming (Avalon-ST) interface）的使用说明，和程序(IP core interface (The Avalon Streaming (Avalon-ST) interface) instructions for use, and procedures)