用VHDL写的运动计时表程序，用Modelsim仿真已经通过，帖出来与大家分享。...

xlinx sparten 3E实验板，实现时钟闹钟功能，闹钟播放电子音乐，时钟，闹钟通过LCD屏显示。自己写的，亲测可用。                                                                                                                    

Quartus环境下使用Verilog编写的HDB3编解码程序，RTL和时序仿真已过(Quartus under the environment of a HDB3 protocol procedures written in Verilog, RTL and timing simulation has be passed)

利用quartus II 软件采用verilog语言设计了一个sigmoid激活函数(this work is a sigmoid ,use verilog language)

nios processor example 1

code for fft non synthesisable in xilinx ise

PLL 锁相环verilog程序 可以直接使用(The PLL can be used directly good use)

说明：  FPGA Verilog浮点数乘法运算，采用单精度浮点型小数格式，运算结果精度可设置，可封装成IP核(FPGA Verilog floating-point multi operation, using single precision floating-point decimal format, the accuracy of the operation results can be set, can be packaged into IP core)

Nonlinear discrete system identification, It uses a pulse of consumer law, Partial least squares method.

Modelsim+DC开发的4级流水线结构的MIPS CPU(mips 4level cpu)

这是一个16位乘法器Verilog程序，包括有符号位和无符号位乘法器(This is a 16-bit multiplier Verilog program, including the sign bit and no sign bit multiplier)