用VHDL写的运动计时表程序，用Modelsim仿真已经通过，帖出来与大家分享。...

Interfacing RTC with spartan 3

verilog 编写基于SRAM(CY7C1041)的代码-Verilog prepared based on the SRAM (CY7C1041) code

设计一个能进行时、分、秒计时的十二小时制或二十四小时制的数字钟，并具有定时与闹钟功能，能在设定的时间发出闹铃音，能非常方便地对小时、分钟和秒进行手动调节以校准时间，每逢整点，产生报时音报时。 实验平台： 1. 一台PC机； 2. MAX+PLUSII10.1。 Verilog HDL语言实现,还有完整的实验报告-The design of a can be hours, minutes, seconds time of 12 hours or 24 hours system, digital clock, and has from time to time with the alarm clock function, can be set to issue a sound alarm can be very convenient to hours, minutes and seconds for manual adjustment to calibrate the time, whenever there is the whole point, resulting in timekeeping timekeeping tone. Experimental platform: 1. A PC machine 2. MAX+ PLUSII10.1. Verilog HDL language, as well as a complete experimental report

rmii 以太网接口时序源代码，值得开发借鉴的哦(verilog hdl)

ofdm的verilog程序 利用ＦＰＧＡ实现-OFDM FPGA using the Verilog procedures realize

RTL8369开发资料，包括手册，图纸，Layout说明等等(RTL8369 development information, including manuals, drawings, Layout Guide.)

VHDL实现交通灯-VHDL traffic lights

开源的ULPI IP核，可用于USB3300芯片的开发(openSource ULPI IP core which could be used for USB3300 chip development)

xillinx Spartan6 FPGA DDR 接口设计指南(xillinx Spartan6 FPGA DDR Interface Design Guidelines)

说明：  1. REVISION HISTORY 2. OVERVIEW 3. SOFTWARE TOOLS AND SYSTEM REQUIREMENTS 4. DESIGN FILE HIERARCHY 5. INSTALLATION AND OPERATING INSTRUCTIONS 6. SUPPORT