SED1330/1335/1336/E1330液晶显示控制器及51汇编源程序.液晶显示程序,显示图形及汉字....

开源软核处理器OpenRisc的SOPC设计

数字信号处理的FPGA实现, 包括了FPGA基础知识，浮点运算，信号处理的FIR FFT等，附录包含源代码(Digital signal processing FPGA implementation, including the basic knowledge of FPGA, floating point operations, signal processing FIR, FFT, etc., the appendix contains the source code)

7段数码显示译码器设计7段数码是纯组合电路，通常的小规模专用IC，如74或4000系列的器件只能作十进制BCD码译码，然而数字系统中的数据处理和运算都是二进制的，所以输出表达都是十六进制的，为了满足十六进制数的译码显示，最方便的方法就是利用译码程序在FPGA/CPLD中来实现。例子作为七段译码器，输出信号LED7S的7位分别接数码管的7个段，高位在左，低位在右。例如当LED7S输出为“1101101”时，数码管的7个段g、f、e、d、c、b、a分别接1、1、0、1、1、0、1；接有高电平的段发亮，于是数码管显示“5”。-7 digital display decoder design 7 Digital is pure combinational circuits, usually of small-scale dedicated IC, such as 74 or 4000 Series devices can only be used to decimal BCD decoder, but digital systems in the data processing and computing are binary, so the output expression are hexadecimal, and hexadecimal number in order to meet the needs of the decoding shows that the most convenient way is to use decoding process in FPGA/CPLD in to achieve. Seven-Segment decoder as an example, the output signal of the seven were LED7S access digital pipe 7 above, high in the left, low in the right. For example, when LED7S output as

endat 2.2 接口内核，发送命令至编码器或从编码器接收位置值(endat 2.2 interface cores, sending commands to the encoder or received the encoder position values)

说明：  NAND FLASH的多个仿真模型，可以用于接口设计的测试(NAND FLASH multiple simulation model that can be used for the test interface design)

基于有限状态机的健壮性测试研究。 关键词：健壮性测试；增强有限状态机；全球平台；安全通道协议(The Research of Robustness Testing Based on FSM)

用 vhdl 语言实现，上下计数器使用边缘触发一个 4 位纹波计数器。积极的边沿触发。 包含的所有文件。试验台架波形。针对采用赛灵思文件

用VerilogHDL写的spi 核的例子(A simple example of SPI core using Verilog HDL)

实现时分秒的计数和校正实现时分秒的计数和校正(Realized and correction of minutes and seconds count)

It is a example about LCD by VHDL code