用VHDL实现视频控制程序(实现对图像的采集和压缩)

FPGA设计攻略及流程，包含时序收敛和引脚约束(FPGA design strategy and process, including time series convergence and pin constraints)

基于BOOTH的32位快速乘法器的设计源码-BOOTH-based 32-bit fast multiplier design source

内插成型滤波器的FPGA实现，可根据需要配置不同的内插倍数，Quarter II环境编译，可直接使用(Interpolation shaping filter FPGA, can be equipped with different interpolation factor, Quarter II compiler environment, can be used directly)

AHB master monitor for verification

UVM 1.2 golden code, (code for UVM, )

除法器,可以很好的实现VHDL除法器的功能对于初学者有很大帮助. -Divider can be very good VHDL divider realize the function of great help for beginners.

verilog实现misp架构，并且支持modelsim仿真(Verilog implements MISP architecture and supports Modelsim simulation)

适用于FPGA的SOPC方面的元器件添加，如COMPNENT-Applicable to FPGA-SOPC area to add components, such as COMPNENT

通过数码管和单片机的组合 制作成的数码管时钟程序(Through the combination of digital control and made ​ ​ into a single-chip digital clock program)

1．初始状态为4个方向的红灯全亮，时间1秒。 2．东、西方向绿灯亮，南、北方向红灯亮。东、西方向通车，时间30秒。 3．东、西方向黄灯闪烁，南、北方向红灯亮。时间2秒。 4．东、西方向红灯亮，南、北方向绿灯亮。南、北方向通车，时间15秒。 5．东、西方向红灯亮，南、北方向黄灯闪烁。时间2秒。 6．返回2，继续运行。 -1. Initial state for four whole direction of the red lights lit up, a second time. 2. East and West to the green, in the south, north to the red light. West and the East to open in time for 30 seconds. 3. East and West to the blinking yellow light, in the south, north to the red light. Time 2 seconds. 4. East and West to the red light, in the south, north to the green. South and North to the opening time of 15 seconds. 5. East and West to the red light, in the south, north to the flashing yellow light. Time 2 seconds. 6. Return 2, continued to operate.