用VHDL实现视频控制程序(实现对图像的采集和压缩)

浮点加法器的用Verilog实现，32位的浮点加法器(Floating point adder Verilog)

本源码为Nios II的开发示例,主要演示Nios II的定时中断器的应用。开发环境QuartusII。 本示例十分经典，对基于SOPC开发的FPGA初学者有很大帮助。-The source code for the Nios II development of an example, the main demonstration Nios II interrupt timing device applications. Development environment QuartusII. This example is very classic, FPGA-based SOPC development of great help for beginners.

例程是基于quartus的，FPGA通过EMIF给DSP发送数据，里面包含了一个简单的状态机和一个基于IP核的fifo，适合初学者(Routine is the FPGA to send data to the DSP via EMIF, which contains a simple state machine and an IP-based core fifo, suitable for beginners)

EDA中很重要的小程序，保证按键可靠性，防止抖动误差信号产生，外部信号输入时必用此消抖函数-EDA very important small procedures to ensure that key reliability and prevent jitter error signal generated, the external input signal must use this function Consumers shiver

altera DE1 SD_CARD带写入一个扇区功能的程序，已确认成功，下载直接运行就可以看效果-altera DE1 SD_CARD with a sector write function procedures, has confirmed the success of running can be downloaded directly watch the effect of

全部通过，是我的精心设计，完全满足初学者的要求。-all passed, I was carefully designed, fully meet the requirements of beginners.

VHDL Code For Full Adder By Data Flow Modelling

FPGA实验_HDB3编码器设计(包含5个模块)(FPGA design experiments _HDB3 encoder (including 5 modules))

说明：  数字钟通过verilog实现，并且支持Modelsim仿真(The digital clock is implemented by Verilog and supports Modelsim simulation)

串口！ 这是一个使用的通信程序 ， 非常好用。(serial port Serial port! This is a communication program used, very useful.)