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vga_demo2
VGA controller : Genarate a VGA signal from your inout information as color info of each pixel
- 2010-06-24 09:26:57下载
- 积分:1
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shuzihongdianlu
数字钟电路的实现,可以24小时计时,可调整时间!(Digital clock circuit implementation, a 24-hour timer, adjustable time!)
- 2013-08-18 14:49:14下载
- 积分:1
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eda技术与vhdl课件,很经典的学习课件
eda技术与vhdl课件,很经典的学习课件-VHDL EDA technology and courseware, it is a classic learning courseware
- 2022-05-18 23:44:31下载
- 积分:1
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volt_mea_disp
本程序是用verilog 编写的模块,用来在lcd1602上显示用tlc549采样的电压值(This program is written in verilog module, used in lcd1602 display with tlc549 sampled voltage value)
- 2013-07-26 00:58:35下载
- 积分:1
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MemoryGame-master
在开发板EGO1上实现的图形记忆游戏,白块按下确认建,黑色块不按确认键(memory game in verilog)
- 2020-12-19 16:29:10下载
- 积分:1
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ac97 VHDL core
ac97 VHDL core
- 2022-04-09 09:46:28下载
- 积分:1
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Bayer2RGB
Bayer 转RGB Verilog代码实现。。5*5 窗口。在工程中应用的(Bayer to RGB Verilog code implementation. 5*5 window. Applied in Engineering)
- 2020-12-14 15:29:15下载
- 积分:1
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HDB3modelsim
HDB3编码通过verilog实现,通过modelsim仿真(HDB3 coding is implemented by Verilog and simulated by Modelsim)
- 2020-06-18 05:20:02下载
- 积分:1
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FM_T
一个简单的FM调制模块,FM发射,用Verilog编写,基于Xilinx SPARTAN6 XC6LX9开发(A simple FM modulation modules for FM transmitter, using Verilog prepared, based on XILINX SPARTAN6 XC6LX9 Development)
- 2020-11-25 20:19:32下载
- 积分:1
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CPU-master
说明: misp,五级流水源码,实现一个建议的cpu(Misp, five-stage flow source code, implementation of a recommended CPU)
- 2020-06-16 00:00:07下载
- 积分:1