veilog code user can derict use it for the base mode.

出租车模块设计加nios2设计cup程序代码 出租车模块设计加nios2设计cup程序代码-Taxi modular design design cup plus nios2 code taxi modular design design cup plus nios2 code

　　本文对数字基带信号脉冲成型滤波的应用、原理及实现进行了研究。首先介绍了数字成型滤波的应用意义并分析了模拟和数字两种硬件实现方法，接着介绍了成形滤波器设计所需要MATLAB软件，以及利用ISE system generator在FPGA上进行滤波器实现的优势。文中给出了成形滤波函数的数学模型，讨论了几种常用成形滤波函数的传输特性以及对传输系统信号误码率的影响。然后介绍了本次设计中使用到的数字成形滤波器设计的几种FIR滤波器结构。把各种设计方案进行仿真，比较仿真结果，最后根据实际应用的情况并结合设计仿真中出现的问题进行分析，得出各种设计结构的优缺点以及适合应用的场合。(In this paper, the application of the principles and implementation of digital baseband signal pulse shaping filter is studied. First introduced the significance of digital shaping filter application and analysis of both analog and digital hardware implementation, then introduces the shaping filter design requires MATLAB software, and the use of ISE system generator on the FPGA to achieve the advantages of the filter. This paper presents a mathematical model of shaping filter function, the transmission characteristics discussed several common shaping filter functions and the impact on the error rate of the signal transmission system. Then introduced the use of this design to several digital shaping filter design FIR filter structure. The various design simulation, compare the simulation results, and finally according to the actual application and combine design simulation to analyze problems, come and where appropriate to the application advantages and disadvantages of various design s)

lattice ECP3系列高速FPGA serdes测试代码(lattice ECP3 series high speed serdes test code)

VHDL经典教程,下了不会后悔-VHDL Tutorial classic, the next will not regret it

关于FFT算法的FPGA实现（源码），数字信号处理不可少。-FFT algorithm on the FPGA implementation (source code)

VHDL数字系统设计和工程实践2，包含原理，真值表和原理图，以及VHDL源代码.-VHDL digital system design and engineering practice, one that contains principles, truth table and schematic, as well as VHDL source code.

The code is used to interface PC monitor with Spartan 3E for the display. if you run the program on spartan 3 you would be able to see different test pattern on the monitor screen

基于7Z010的触摸屏驱动程序.开发板使用的是Xilinx公司的Zynq7000 系列的芯片， 型号为XC7Z010-1CLG400C， 400 个引脚的 FBGA 封装。 ZYNQ7000 芯片可分成处理器系统部分 Processor System（PS） 和可编程逻辑部分 Programmable Logic（PL）。 在 AX7010 开发板上，ZYNQ7000 的 PS 部分和 PL 部分都搭载了丰富的外部接口和设备，方便用户的使用和功能验证。(Touch screen driver based on 7z010)

VHDL子程序集,包括各种例程资料以及源码.-VHDL subprogram, including a variety of routine information as well as the source.

verilog编写的QPSK发射机的ＦＰＧＡ部分，已经过验证，完全达到要求。调制矢量误差４％(QPSK transmitter verilog prepared by the FPGA portion, has been proven, fully meet the requirements. Modulation vector error of 4 )