veilog code user can derict use it for the base mode.

SDRAM的vegilog代码，做一个SDRAM的封装成为SRAM一样进行操作。一个顶层文件下由三个模块-SDRAM

一组练习，关于VHDL的一些基础的知识和练习可以参考一些具体的问题-A group of exercises, on a number of VHDL-based knowledge and practice can refer to some specific questions

modelsim教程仅供学习-modelsim tutorial to learn only

FPGA 设计的四种常用思想与技巧-FPGA design ideas and techniques used in four

用verilog实现的UDP协议，包括arp，udp，ip分段协议等，对于想用FPGA实现TCP/IP协议的人来说，应该会起到一定的帮助作用(Implemented with verilog UDP protocols, including arp, udp, ip fragmentation protocol, etc., who want to achieve TCP/IP protocol with the FPGA people, should play a helpful role)

高精度直流信号源，DAC1220，20位分辨率，双极性输出(High-precision DC source, DAC1220,20 bit resolution, bipolar output)

本程序是用vhdl开发的实现并串转换功能的程序。(This procedure is developed using VHDL implementation and string conversion function of the program.)

RS编码器在fpga上的实现，用的modelsim开发环境(RS encoder in the realization of the fpga, development environment used in modelsim)

designing of 16 bit adder using 4 bit adder using verilog code

说明：  100个vhdl例子，对初学者很有用，可以用MAX+PLUS 2来编译仿真的(100 vhdl example, useful for beginners, you can use the MAX+ PLUS 2 to compile the simulation)