SATA数据传输控制程序

采用dds产生3路正弦波作为调制波，一路三角波形作为高频载波，按照spwm原理让正弦波和三角波送入比较器做比较判决运算。并且调制波和载波相位频率可调，外部按键调试即可。verilog实现，在altera的fpga芯片运行通过。

VGA显示原理与VGA时序实现论文,详细介绍了VGA的原理 (Principle and VGA VGA display timing to achieve paper, detailing the principles VGA)

改VHDL代码可以实现超声波测距的功能，其精确度达到US级，可以用七段数码管显示其数值(sound ranging sound ranging sound ranging sound ranging sound ranging sound ranging sound ranging sound ranging sound ranging sound ranging sound ranging )

华为文档《硬件描述语言Verilog基础》-目录 原来搞VHDL，刚刚开始学Verilog。觉得这个入门的提纲不错，共享一下。 (Huawei Documents " basic Verilog Hardware Description Language" - the original directory engage in VHDL, just beginning to learn Verilog. Feel that the entry of the outline of a good, share some.)

adc0809 转换，verilog代码(adc0809 conversion, verilog code)

时序约束方面的经典文章，适合学习FPGA的初学者(A classic article on timing constraints, suitable for beginners to learn FPGA)

VHDL实现国家SM4加密算法（ECB）模式 (VHDL to achieve national SM4 encryption algorithm (ECB) mode)

说明：  1、能正确显示输入信号频率； 2、测量频率范围为1Hz ~ 999999Hz； 3、测量结果以十进制数字显示； 4、能测量幅值较小的信号频率； 5、有自动刷新输出数据的功能（如5s刷新一次）； 6、有自检模块（如产生100Hz的校准方波）；(1. It can correctly display the input signal frequency; 2. The frequency range of measurement is 1Hz ~ 99999hz; 3. The measurement results are displayed in decimal; 4. It can measure signal frequency with small amplitude; 5. It has the function of automatically refreshing the output data (e.g. once in 5S); 6. Self checking module (such as generating 100Hz calibration square wave);)

说明：  以ISE为开发环境，Verilog语言编写程序。功能：FPGA控制 LCD_1602动态显示秒表(In the development environment of ISE, Verilog language is used to write programs. Function: LCD_1602 dynamic display stopwatch controlled by FPGA)

基于System Generator的图像处理工程,多媒体处理FPGA实现的源码,图像形态学部分,腐蚀,膨胀,细化算法(System Generator based image processing engineering, multimedia processing FPGA implementation source code, image morphology section, corrosion, swelling, thinning algorithm)