用VHDL写的4*4乘法器，学习VHDL语言的可以

LDPC码的短循环对LDPC码性能的影响 (Short Protograph-Based LDPC Codes)

sdram controller vhdl

this project is based on 2*1 and 4*1 multiplexer and 1*2 and 1*4 demultiplexer using vhdl.this is the 100 correct code,reference is taken from book digital electrionics written by anand kumar.please use quatrus to access this code.this code can be used for the final year project for engineering. Here dataflow techniques and behavioural -this project is based on 2*1 and 4*1 multiplexer and 1*2 and 1*4 demultiplexer using vhdl.this is the 100 correct code,reference is taken from book digital electrionics written by anand kumar.please use quatrus to access this code.this code can be used for the final year project for engineering. Here dataflow techniques and behavioural

BISS-B 源代码。包含传感器模式和寄存器模式(BISS-B source code. Includes sensor mode and register mode)

能够在EDA环境下实现四位十进制数字密码锁的设置与开锁功能，并能更改使用密码，还可以防止抖动(EDA environment to achieve four decimal code lock and unlock function of the settings and change the use of passwords, but also to prevent the jitter)

具有16个校验位的RS编码器，在FPGA上实现。(With 16 RS encoder, the parity bit in the FPGA.)

基于SHA-1算法和DS28E01加密芯片的FPGA系统设计，该上传文件为整个设计的系统文件。Quarter软件编程的Verilog程序，包含仿真调试界面。(Design of FPGA system based on SHA-1 algorithm and DS28E01 encryption chip。)

方案组成模块及系统框图 本方案设计主要由以下模块组成 1：顶层模块 2：数据输入排序模块 3：系统控制模块 4：RAM控制器模块 5：ROM控制器模块 6：蝶型单元模块(Program composition module and system diagram The design of this scheme is mainly composed of the following modules 1: top module 2: data input sorting module 3: system control module 4:RAM controller module 5:ROM controller module 6: butterfly type unit module)

说明：  学习VHDL可以用得上，有很多实例，可以对照着自己写一些东西(VHDL can be useful to learn, there are many examples, can be done to write something)

实现SIGMA-DELTA Modulator的veriolog代码(sigma-delta moudulator for RFPLL )