用VHDL写的4*4乘法器，学习VHDL语言的可以

密码锁verilog源代码，包括四个七段数码管显示模块，设置密码以及输入密码校验模块(Password lock Verilog source code, including four of seven digital tube display module, set the password and password verification module)

verilog file , FPGA controll vga display- verilog file , FPGA controll vga display

vhdl code for programming

matlab仿真MATLAB电机仿真精华50例--源代码异步电机\asymotor_stator.mdl

Verilog code for RS-(255,239) encoder.

基于可编程逻辑器件FPGA的独立式键盘设计，内部具有硬件去抖动电路。值得一看-FPGA-based programmable logic device stand-alone keyboard design, the internal hardware to jitter circuit. Worth a visit

CMV2000的对齐模块，适用于其他对齐模块，自行修改(CMV2000 alignment module, suitable for other alignment modules, self-modifying)

出租车的计费功能的实现,计量模块、计费模块、控制模块、译码模块。(taxi fee)

基于System Generator的图像处理工程,多媒体处理FPGA实现的源码,基于视频的运动检测(System Generator based image processing engineering, multimedia processing on FPGA source code, based on video motion detection)

How to Connecting Xilinx FPGAs to the Philips