用VHDL写的4*4乘法器，学习VHDL语言的可以

六十进制计数器，显示0到60.可以用数码管显示。(Six decimal counter 0-60 can use the digital display.)

实现十六位加法器，是书籍上配套的应该可用-This is an 16 bit adder using vhdl

光纤通道协议，包括FC-SW,FC-FS,FC-LS,FC-GS,FC-HBA,FC-AE-ASM等文档。 (Fibre Channel protocols, including FC-SW, FC-FS, FC-LS, FC-GS, FC-HBA, FC-AE-ASM and other documents.)(Fiber channel protocol, including FC-SW, FC-FS, FC-LS, FC-GS, FC-HBA, FC-AE-ASM and other documents. (Fibre Channel protocols, including FC-SW, FC-FS, FC-LS, FC-GS, FC-HBA, FC-AE-ASM and FC-AE-ASM))

讲述4ASK的原理并附有matlab调制解调的源码。。。。。。。。。。 注：原来上传的4ASKmod.zip不要下(The principle tells 4ASK together with modulation and demodulation matlab source. . . . . . . . . . Note: The original upload 4ASKmod.zip not down)

32-bit shifter, shifter, 32-bit.Very goog as a study file.

VHDL tutorial for self studying

在FPGA硬件上，使用verilog语言编写的一个乘累加器程序。(FPGA hardware, a multiply accumulator verilog language program.)

说明：  一个简单的键盘接口模块程序，对键盘输入的数据和时钟信号进行过滤。过滤后的数据信号PS2Df将被送入两个11位移位寄存器中(A simple keyboard interface module program filters keyboard input data and clock signals. The filtered data signal PS2Df will be fed into two 11-bit displacement registers.)

用Verilog实现一个基于Mesh拓扑结构的路由器网络(Using Verilog to implement a router network based on Mesh topology)

spi通用串行总线，4线控制，可读写操作(SPI universal serial bus, 4-wire control, readable and writable operation)