用VHDL写的4*4乘法器，学习VHDL语言的可以

说明：  URISC的RTL级设计，Verilog代码(Design: URISC RTL Verilog)

说明：  这是一个关于OQPSK的Matlab程序 这是一个关于OQPSK的Matlab程序 (This is a OQPSK the Matlab program is a program of OQPSK in Matlab)

Verilog Language Manual

实现数字变下频的matlab程序，CIC,HB,FIR滤波器代码都在其中(Realize digital variable frequency under matlab, CIC, HB, FIR filter code in it )

FPGA中针对Biss通讯协议解码VHDL语言源码(FPGA communication protocols against BiSS source decoder VHDL language)

一种实现计算机接口rs232与FPGA通信的基于VHDL语言设计的一段非常简洁的程序(A RS232 computer interface implementation with FPGA-based VHDL language communications designed a very simple procedure)

采用CORDIC算法的直接数字频率合成器的设计(CORDIC algorithm uses direct digital frequency synthesizer design)

verilg语言实现测频 及与stm32以fsmc通信方式进行通信(Verilg to achieve frequency measurement and communication with STM32 in FSMC communication mode)

在学习verilog 中与遇到一些列问题的整理。(this Documentation is about the problem about verilog which is meeted when i was learn FPGA)

数字频率计毕业论文 不是自己做的-Digital Cymometer thesis do not own. . Ha ha