MPEG

驱动8*8点阵块显示汉字，可以自己根据要显示的内容随意更改，已通过验证。(Blocks of 8* 8 dot matrix drive display Chinese characters, you can display the content according to their random changes, has been verified.)

RISC 5级流水线CPU，带HAZARD处理(RISC 5 pipeline CPU with HAZARD processing)

We present elliptic curve cryptography (ECC) coprocessor, which is dual-field processor with projective coordinator. We have implemented architecture for scalar multiplication, which is key operation in elliptic curve cryptography. Our coprocessor can be adapted both prime field and binary field, also contains a control unit with 256 bit serial and parallel operations , which provide integrated highthroughput with low power consumptions. Our scalar multiplier architecture operation is perform base on clock rate and produce better performance in term of time and area compared to similar works. We used Verilog for programming and synthesized using Xilinx Vertex II Pro devices. Simulation was done with Modelsim XE 6.1e, VLSI simulation software from Mentor Graphics Corporation especially for Xilinx devices.

fpga里实现 uart 经典 vhdl语言写的 ise工程文件-fpga implementation in vhdl language classic uart of ise project file

基于System Generator的图像处理工程,多媒体处理FPGA实现的源码,基于视频的运动跟踪(System Generator based image processing engineering, multimedia processing on FPGA source, video-based motion tracking)

FPGA开发仿真工具modelsim的高级进阶教程，包括如何写脚本文件和后台批处理文件(FPGA Development Advanced simulation tools modelsim tutorial, including how to write a script file and back-office batch file)

vhdl code for counterand detemines how counter works

同步fifo的调用程序，调用Quartus II 9.0 (32-Bit)中的fifo模块(Synchronous fifo calling program, call Quartus II 9.0 (32-Bit) in fifo module)

是用VHDL语言写的对A/D转换模块的控制程序，希望对大家有帮助。-VHDL language is used on the A/D conversion module control procedures, in the hope that everyone has to help.

基于Montgoery 算法的RSA,FPGA verilog 实现，有测试文件(Based on Montgoery algorithm for RSA,FPGA verilog implementation，bench file)