VHDL出租车计价器，包含所有代码及其仿真结果

Commponent for drivering EEPROM memory AT25320 from Avalon bus.

实现arm与fpga之间通过gpmc总线通信(the device of fpga)

verlog hdl无刷电机控制程序,已在modelsim仿真-verlog hdl brushless motor control procedures have been in ModelSim Simulation

Coding Styles for if Statements and case Statements

次源码实现一个扩频接收机系统，用VHDL语言编写，并且有完整得测试程序-Second source to achieve a spread spectrum receiver system, using VHDL language, and have a complete test procedure was

同步FIFO功能，verilog语言描述，通过了modelsim 6.0 仿真，Quartue综合-Synchronous FIFO function, verilog language described by the modelsim 6.0 simulation, Quartue integrated

使用verilog语言编写的异步串口模块，带有16级深的FIFO，它与DSP28335的SCI相似，可以帮助初学者更快地理解FPGA和DSP的硬件结构和编程思路(Use verilog language of asynchronous serial port module, FIFO with deep level 16, it was similar with DSP28335 SCI, can help beginners to understand faster the FPGA and DSP hardware structure and programming ideas)

UART RS232 IPCORE for sopc builder -RS232 UART IPCORE for sopc builder

考研复试口语，适合计算机专业考研复试口语专业课(Traditional Interview spoken, spoken for Specialized Computer Traditional Interview)

pid程序,新学者，使用FPGA学习，希望大家一起学习