这是个的VHDL点亮LED的程序，大家一齐分享吧

adder_array的设计。加法器阵列设计，顶层模块，四步流水，21位(adder_array the design. The adder array design, top-level module, four-step pipeline, 21)

this example finds the gapes that are existed in a word

FPGA与DSP的EMIFA口接口程序.在FPGA内分配了两块双BUFFER与DSP进行通信.-FPGA and DSP EMIFA mouth interface program. The FPGA distribution within the two-SUBJECT ER and DSP communication.

Anticipated Adder for Xilinx

汉明码转换，在FPGA上用verilog实现(hamming encoder, using FPGA)

说明：  之前一直找不到自学编写了一个，PID案例，分享下(I have been unable to find a self-taught, compiled a PID case, share under)

电子书籍 verilog HDL 数字设计与综合 夏宇闻所编写(electronic text Foreign electronic and communication textbooks)

VHDL Project for beginners. Electronic dice game. Perfect for Spartan devices.

I2C 控制器的 Verilog源程序2(I2C controller Verilog source 2)

等精度频率计的verilogHDL的实现,我花了好长时间才写的哦