这是个的VHDL点亮LED的程序，大家一齐分享吧

register file in vhdl and alu

fpga下的七段数码管显示 大 学 实 验 报 告-fpga under the seven-segment digital tube experiment reports that the University

该工程文件实现ARM系统中CPLD的逻辑工作，起到外围资源的逻辑地址译码功能-realization of the project document ARM system CPLD logic, external resources have address decoding logic function

说明：  Verilog 入门,如果你要很了解Verilog你不用先谖完一本厚厚的书还弄不清楚Verilog到底在干啥事,这份资料有助於快速了斛Verilog(Verilog Basic, If you try very hard to understand verilog by read a thick book, try read this first you will get a quick understanding of verlog.)

nios学习资料，fpga调用外部sdram实例，值得初学者下载。(nios learning materials, fpga call external sdram instance, it is worth beginners to download.)

VHDL电梯控制器程序设计与仿真，内含原理图和VHDL源码，有助于学习VHFL(VHDL u7535 u68AF u63A7 u5236 u5668 u7A0B u5E8F u8BBE u8BA1 u4E0E u4EFF u771F)

turbo码的verilog程序，有意者请下载。(turbo code verilog procedures Interested parties please download.)

ofdm_cp_insertion add/remove CP

system Verilog combinational logic

A simple Manchester Encoder to convert serial data to Manchester encoded data.