基于FPGA状态机实现的I2C Verilog工程

说明：  QPSK的解调程序，采用Verilog编写而成(QPSK demodulation program, written by Verilog)

1、FSMC全称是静态存储控制器，用来高速操作外部SRAM，NOR，NAND等，广泛用来驱动LCD MCU的FSMC配置在fsmc_nor.c，你也可以查阅相关资料。 2、此例程通过读写外部M29W128，熟悉FSMC的配置以及操作。(1, FSMC stands for static memory controller for high-speed operation of external SRAM, NOR, NAND, widely used to drive the LCD MCU FSMC configuration in fsmc_nor.c, you can also access to relevant information. This routine by reading and writing external M29W128 familiar with the configuration and the operation of the FSMC.)

adc0809 转换，verilog代码(adc0809 conversion, verilog code)

应用背景Project: A Wishbone Controlled Real--time Clock Core Purpose: Implement a real time clock, including alarm, count--down timer, stopwatch, variable time frequency, and more.关键技术基于FPGA的用verilog编写的时钟模块，具有时间计数，闹铃，以及计数器功能！具有很好的学习和使用价值。基于FPGA的用verilog编写的时钟模块，具有时间计数，闹铃，以及计数器功能！具有很好的学习和使用价值。

说明：  VHDL语言写的SRAM控制程序，在开发板上验证过。(Written in VHDL SRAM control procedures, the development board verified.)

自写的巴克频带滤波器组代码，生成频带滤波器组。内涵debug：输出生成的滤波器(Barker band filter bank code that generates band filter bank. Connotation debug: output generated filter)

说明：  基于Verilog语言编写的LCD1602显示的日历程序，类似时钟功能值得参考。(LCD1602 shows calendar program based on Verilog language, similar clock function is worth reference.)

本文介绍一种波导双模双带滤波器的设计方法。(This paper presents a new class of dual-mode dualband filters in which each polarization is dedicated to a selected band. The equivalent circuit is a parallel combination of two inline networks that represent each polarization. A transmission zero is generated between the two bands by properly adjusting the relative orientations of the input and output coupling apertures.)

注意：是verilog语言写的 一bit的全加器，实现4位数的串行加法器，一个时钟能完成一次一bit的全加(Note: It is verilog language to write a bit full adder, to achieve four-digit serial adder, a clock can be completed once a bit full adder)

有三个基于FPGA驱动高速AD/DA的程序、硬件电路图、使用向导手册、连接方法，支持ADDA_AX301，ADDA_AX415，ADDA_DB2C8，可以下载到 FPGA 黑金开发板、FPGA 黑金开发板学生版结合相关模块进行使用，