基于FPGA状态机实现的I2C Verilog工程

verilog实现的LMS的算法，另外有tb文件可以测试已测试代码正确……(verilog implementation of LMS algorithm, another tb files can test the code has been tested properly ......)

数字时钟管理器，xilinx公司开发板集成时钟，实现分频、倍频等功能。(Digital clock managers, xilinx development board integrated clock divider, multiplier, and other functions.)

74hc595 driver 8 led

说明：  verilog语言编写的dac5687的接口程序，串行模式控制。(written dac5687 verilog interface program, serial mode control.)

FPGA的经典例程，可以进行移植和借鉴使用(FPGA' s classic routines, can be transplanted and learn to use)

说明：  利用ISE编写的产生WALSH码的verilog程序，简单易懂，稍稍修改就可以产生出自己想的8 16 32 64位的WALSH码。。(Prepared using ISE verilog code generated WALSH procedures, easy to understand, a little modification can generate their own like the 8,16，32，64-bit code WALSH. .)

产生高斯最小相移键控信号的阐述仿真，包括调制解调、信道模型等。(Simulation program to realize GMSK transmission system)

说明：  该文件包含了实现单周期cpu的全部代码以及实验报告，包括仿真波形以及烧板过程(This file contains all the codes and experimental reports of realizing single cycle CPU, including simulation waveform and download process)

对数计算源程序，能够在FPGA中计算某数的对数(Determined on the basis of the source, calculated in the FPGA to a certain number of log)

应用背景ADPLL数字锁相环在fpga上工程中有广泛的应用，程序有verilog语言编写关键技术全数字锁相环ADPLL由verilog HDL语言编写在FPGA上使用。